MPC8280 datasheet(596/1386 Pages) FREESCALE

596 / 1386 page

Serial Interface with Time-Slot Assigner

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

15-18

Freescale Semiconductor

Table 15-5 describes SIxMR fields.

34567

Field

—

SADx

SDMx

RFSDx

DSCx CRTx

SLx

CEx

FEx

GMx

TFSDx

Reset

0000_0000_0000_0000

R/W

Addr

11B20 (SI1AMR), 11B22 (SI1BMR), 11B24 (SI1CMR), 11B26 (SI1DMR)/

11B40 (SI2AMR), 11B42 (SI2BMR), 11B44 (SI2CMR), 11B46 (SI2DMR)

Figure 15-11. SI Mode Registers (SI

xMR)

Table 15-5. SI

xMR Field Descriptions

Bits

Name

Description

—

Reserved. Should be cleared.

1–3

SADx

Starting bank address for the RAM of TDM a, b, c or d. These three bits define the starting bank

address of the SI

x RAM section that belongs to TDMx channel.

Note: As noted previously, the SI

x RAM contains four banks of 64 entries for receive and four banks

of 64 entries for transmit. The starting bank address of each TDM can be programmed with a

granularity of 32 entries. The user can put the shadow RAM section of the same TDM on the

same bank, but the user cannot put two different TDMs on the same bank.

The last entry of a certain TDM is determined by the LST bit in the SI

x RAM entry. The user must set

LST within the entries of SI

x RAM blocks for every TDM used, that is, before the starting address of

the next TDM.

000 First bank, first 32 entries

001 First bank, second 32 entries

010 Second bank, first 32entries

011 Second bank, second 32 entries

100 Third bank, first 32 entries

101 Third bank, second 32 entries

110 Fourth bank, first 32 entries

111 Fourth bank, second 32 entries

4–5

SDMx

SI Diagnostic Mode for TDM a, b, c or d

00 Normal operation.

01 Automatic echo. In this mode, the TDM transmitter automatically retransmits the TDM received

data on a bit-by-bit basis. The receive section operates normally, but the transmit section can only

retransmit received data. In this mode, the L1GRx line is ignored.

10 Internal loopback. In this mode, the TDM transmitter output is internally connected to the TDM

receiver input (L1TXDx is connected to L1RXDx). The receiver and transmitter operate normally.

The data appears on the L1TXDx pin and in this mode, L1RQ

x is asserted normally. The L1GRx

line is ignored.

11 Loopback control. In this mode, the TDM transmitter output is internally connected to the TDM

receiver input (L1TXDx is connected to L1RXDx). The transmitter output (L1TXDx) and L1RQ

are inactive. This mode is used to accomplish loopback testing of the entire TDM without affecting

the external serial lines.

Note: In modes 01, 10, and 11, the receive and transmit clocks should be identical.

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