MPC8280 datasheet(630/1386 Pages) FREESCALE

630 / 1386 page

CPM Multiplexing

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

16-18

Freescale Semiconductor

SC3

SCC3 connection

0 SCC3 is not connected to the TSA and is either connected directly to the NMSIx pins or is not

used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O

control register.

1 SCC3 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.

18–20

RS3CS Receive SCC3 clock source (NMSI mode). Ignored if SCC3 is connected to the TSA (SC3 = 1).

000 SCC3 receive clock is BRG1.

001 SCC3 receive clock is BRG2.

010 SCC3 receive clock is BRG3.

011 SCC3 receive clock is BRG4.

100 SCC3 receive clock is CLK5.

101 SCC3 receive clock is CLK6.

110 SCC3 receive clock is CLK7.

111 SCC3 receive clock is CLK8.

21–23

TS3CS

Transmit SCC3 clock source (NMSI mode). Ignored if SCC3 is connected to the TSA (SC3 = 1).

000 SCC3 transmit clock is BRG1.

001 SCC3 transmit clock is BRG2.

010 SCC3 transmit clock is BRG3.

011 SCC3 transmit clock is BRG4.

100 SCC3 transmit clock is CLK5.

101 SCC3 transmit clock is CLK6.

110 SCC3 transmit clock is CLK7.

111 SCC3 transmit clock is CLK8.

GR4

Grant support of SCC4

0 SCC4 transmitter does not support the grant mechanism. The grant is always asserted internally.

1 SCC4 transmitter supports the grant mechanism as determined by the GMx bit of a serial device

channel.

SC4

SCC4 connection

0 SCC4 is not connected to the TSA and is either connected directly to the NMSIx pins or is not

used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O

control register.

1 SCC4 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.

Table 16-6. CMXSCR Field Descriptions (continued)

Bits

Name

Description

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