MPC8280 datasheet(641/1386 Pages) FREESCALE

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Timers

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

18-3

The restart gate mode performs the same function as normal mode, except it also resets the counter on the

falling edge of TGATEx. This mode has applications in pulse interval measurement and bus monitoring as

follows:

•

Pulse measurement—The restart gate mode can measure a low TGATEx. The rising edge of

TGATEx completes the measurement and if TGATEx is connected externally to TINx, it causes the

timer to capture the count value and generate a rising-edge interrupt.

•

Bus monitoring—The restart gate mode can detect a signal that is abnormally stuck low. The bus

signal should be connected to TGATEx. The timer count is reset on the falling edge of the bus

signal and if the bus signal does not go high again within the number of user-defined clocks, an

interrupt can be generated.

The gate function is enabled in the TMR; the gate operating mode is selected in the TGCR.

NOTE

TGATEx is internally synchronized to the system clock. If TGATEx meets

the asynchronous input setup time, the counter begins counting after one

system clock when working with the internal clock.

18.2.1

Cascaded Mode

In this mode, two 16-bit timers can be internally cascaded to form a 32-bit counter. Timer 1 may be

internally cascaded to timer 2, and timer 3 can be internally cascaded to timer 4. Because the decision to

cascade timers is made independently, the user can select two 16-bit timers or one 32-bit timer. TGCR is

used to put the timers into cascaded mode, as shown in Figure 18-2.

Figure 18-2. Timer Cascaded Mode Block Diagram

If TGCR[CAS] = 1, the two timers function as a 32-bit timer with a 32-bit TRR, TCR, and TCN. In this

case, TMR1 and/or TMR3 are ignored, and the modes are defined using TMR2 and/or TMR4. The capture

is controlled from TIN2 or TIN4 and the interrupts are generated from TER2 or TER4. In cascaded mode,

the combined TRR, TCR, and TCN must be referenced with 32-bit bus cycles.

18.2.2

Timer Global Configuration Registers (TGCR1 and TGCR2)

The timer global configuration registers (TGCR1 and TGCR2), shown in Figure 18-3 and Figure 18-4,

contain configuration parameters used by the timers. These registers allow simultaneous starting and

stopping of a pair of timers (1 and 2 or 3 and 4) if one bus cycle is used.

Timer1

Timer2

Timer3

Timer4

Capture

Clock

TRR, TCR, TCN connected to D[16–31]

TRR, TCR, TCN connected to D[0–15]

TRR, TCR, TCN connected to D[16–31]

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