MPC8280 datasheet(643/1386 Pages) FREESCALE

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Timers

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

18-5

The TGCR2 register is shown in Figure 18-4.

Table 18-2 describes TGCR2 fields.

18.2.3

Timer Mode Registers (TMR1–TMR4)

The four timer mode registers (TMR1–TMR4) are shown in Figure 18-5.

Erratic behavior may occur if TGCR1 and TGCR2 are not initialized before the TMRs. Only TGCR[RST]

can be modified at any time.

01234567

Field

CAS4

—

STP4

RST4

GM2

—

STP3

RST3

Reset

0000_0000

R/W

Addr

0x10D84

Figure 18-4. Timer Global Configuration Register 2 (TGCR2)

Table 18-2. TGCR2 Field Descriptions

Bit

Name

Description

CAS4

Cascade timers.

0 Normal operation.

1 Timers 3 and 4 cascades to form a 32-bit timer.

—

Reserved, should be cleared.

STP 4

Stop timer.

0 Normal operation.

1 Reduce power consumption of the timer. This bit stops all clocks to the timer, except the clock

from the internal bus interface, which allows the user to read and write timer registers. The clocks

to the timer remain stopped until the user clears this bit or a hardware reset occurs.

RST4

Reset timer.

0 Reset the corresponding timer (a software reset is identical to an external reset).

1 Enable the corresponding timer if the STP bit is cleared.

GM2

Gate mode for TGATE2. This bit is valid only if the gate function is enabled in TMR3 or TMR4.

0 Restart gate mode. TGATE2 is used to enable/disable the count. The falling edge of TGATE2

enables and restarts the count and the rising edge of TGATE2 disables the count.

1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE2 does not

restart the count value in TCN.

—

Reserved, should be cleared.

STP3

Stop timer.

0 Normal operation.

1 Reduce power consumption of the timer. This bit stops all clocks to the timer, however it is

possible to read the values while the clock is stopped. The clocks to the timer remain stopped

until the user clears this bit or a hardware reset occurs.

RST3

Reset timer.

0 Reset the corresponding timer (a software reset is identical to an external reset).

1 Enable the corresponding timer if STP = 0.

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