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MPC8280 Datasheet(PDF) 646 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 646 Page - Freescale Semiconductor, Inc |
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646 / 1386 page ![]() Timers MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 18-8 Freescale Semiconductor Writing ones clears event bits; writing zeros has no effect. Both event bits must be cleared before the timer negates the interrupt. Table 18-4 describes TER fields. 0 13 14 15 Field — REF CAP Reset 0x0000 Addr 0x10DB0 (TER1); 0x10DB2 (TER2); 0x10DB4 (TER3); 0x10DB6 (TER4) Figure 18-9. Timer Event Registers (TER1–TER4) Table 18-4. TER Field Descriptions Bits Name Description 0–13 – Reserved, should be cleared. 14 REF Output reference event. The counter has reached the TRR value. TMR[ORI] is used to enable the interrupt request caused by this event. 15 CAP Capture event. The counter value has been latched into the TCR. TMR[CE] is used to enable generation of this event. |
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