MPC8280 datasheet(650/1386 Pages) FREESCALE

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SDMA Channels and IDMA Emulation

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

19-4

Freescale Semiconductor

19.2.2

SDMA Mask Register (SDMR)

The SDMA mask register (SDMR) is an 8-bit read/write register with the same bit format as the SDMA

status register. If an SDMR bit is 1, the corresponding interrupt in SDSR is enabled. If the bit is zero, the

corresponding interrupt in the status register is masked. SDMR is cleared at reset. SDMR can be accessed

at 0x1101C.

19.2.3

SDMA Transfer Error Address Registers (PDTEA and LDTEA)

There are two 32-bit, read-only SDMA address registers. The PDTEA holds the system address accessed

during an SDMA transfer error on the 60x bus. The LDTEA holds the system address accessed during an

SDMA transfer error on the local/PCI bus. LDTEA is constantly updated with memory address of the local

bus access regardless of whether SDMA error on the local bus has occurred. The address value inside

LDTEA stops updating when SDSR[SBRE_L] is asserted. Both registers are undefined at reset. PDTEA

can be accessed at 0x10050; LDTEA can be accessed at 0x10058.

19.2.4

SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM)

There are two SDMA transfer error MSNUM registers (PDTEM and LDTEM). MSNUM[0–4] contains

the sub-block code (SBC) used to identify the current peripheral controller accessing the bus. MSNUM[5]

identifies which half of the controller is transferring (transmitter or receiver). The MSNUM of each

transaction is held in these registers until the transaction is complete.

PDTEM is for SDMA transfer errors on the 60x bus, and LDTEM is for errors on the local/PCI bus. Both

registers are undefined at reset. See Figure 19-4.

Table 19-2 describes PDTEM and LDTEM fields.

012

Field

—

MSNUM 1

Reset

—

R/W

Addr

0x10054 (PDTEM); 0x1005C (LDTEM)

1 On .29µm (HiP3), Rev A.1 devices, MSNUM = [0–5]. For .25µm (HiP4) and all other .29µm devices, MSNUM = [2–6].

Figure 19-4. SDMA Transfer Error MSNUM Registers (PDTEM/LDTEM)

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