MPC8280 datasheet(651/1386 Pages) FREESCALE

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SDMA Channels and IDMA Emulation

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

19-5

19.3

IDMA Emulation

The CPM can be configured to provide general-purpose DMA functionality through the SDMA channel.

Four general-purpose independent DMA (IDMA) channels are supported. In this special emulation mode,

the user can specify any memory-to-memory or peripheral-to/from-memory transfers as if using dedicated

DMA hardware.

The general-purpose IDMA channels can operate in different user-programmable data transfer modes. The

IDMA can transfer data between any combination of memory and I/O. In addition, data may be transferred

in either byte, half-word, word, double-word or burst quantities (note that IDMA cannot burst to or from

the dual-port RAM) and the source and destination addresses may be odd or even. The most efficient

packing algorithms are used in the IDMA transfers; however, anytime the IDMA has 0x10 or more bytes

to transfer, it will burst. The single-address mode (fly-by mode) gives the highest performance, allowing

data to be transferred between memory and a peripheral in a single bus transaction. The chip-select and

wait-state generation logic on the MPC8280 can be used with the IDMA.

The bus bandwidth occupied by the IDMA can be programmed in the IDMA parameter RAM to achieve

maximum system performance.

The IDMA supports two buffer handling modes—auto buffer and buffer chaining. The auto buffer mode

allows blocks of data to be repeatedly moved from one location to another without user intervention. The

buffer chaining mode allows a chain of blocks to be moved. The user specifies the data movement using

BD tables like those used by other peripheral controllers. The BD tables reside in the dual-port RAM.

Each IDMA has three signals (DREQx, DACKx and DONEx) for peripheral handshaking.

19.4

IDMA Features

The main IDMA features are as follows:

•

Four independent, fully programmable DMA channels

•

Dual- or single-address transfers with 32-bit address and 64-bit data capability

•

Memory-to-memory, memory-to-peripheral, and peripheral-to-memory modes

Table 19-2. PDTEM and LDTEM Field Descriptions

Bits1

1 Bit ranges are for .29µm (HiP3) Rev B.3, C.2 and .25µm (HiP4) devices. For .29µm Rev A.1 devices, refer to notes 2–4.

Name

Description

0–1

—2

2 On .29µm Rev A.1 devices, [6–7].

Reserved, should be cleared.

2–6

MSNUM[2–6]3

3 On .29µm Rev A.1 devices, MSNUM[0–4].

Bits 2–63 of MSNUM is the sub-block code of the current peripheral controller accessing the bus.

See the SBC field description of the CPCR in Section 14.4.1, “CP Command Register (CPCR).”

MSNUM[7]4

4 On .29µm Rev A.1 devices, MSNUM[5].

Bit 74 of MSNUM indicates which section of the peripheral controller is accessing the bus.

0Transmit section

1 Receive section

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