MPC8280 datasheet(654/1386 Pages) FREESCALE

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SDMA Channels and IDMA Emulation

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

19-8

Freescale Semiconductor

Figure 19-6 shows an example of the three IDMA transfer stages.

Figure 19-6. Example IDMA Transfer Buffer States for a Memory-to-Memory Transfer

(Size = 128 Bytes)

19.5.1.1

External Request Mode

Memory-to-memory transfers can be configured to operate in external request mode (DCM[ERM] = 1).

In external request mode, every read transfer is triggered by the assertion of DREQ. When the transfer

buffer is full, the first write transfer is done automatically. Additional write transfers, if needed, are

triggered by DREQ assertions. Because at least one of the transfer sizes (STS or DTS) equals SS_MAX,

every DREQ assertion causes one transfer to the smaller (in STS/DTS terms) bus. If STS = DTS, asserting

DREQ triggers one read transfer automatically followed by one write transfer.

NOTE

External request mode does not support external DONE signaling from a

device and DACK signaling from an IDMA channel.

First Phase

after first read

after first write

after second read

after second write

after third read

after third write

Steady-State Phase (2 transfers in this case)

Last Phase

after last read

after last write

Read size = EOB(source) + SS_MAX

Write size = EOB(destination) + SS_MAX

Read size = SS_MAX

Write size = SS_MAX

Read size = remainder data of BD

Write size = all data left

EOB (source)

EOB (destination)

128

Read size = SS_MAX

Write size = SS_MAX

Note: After phase 1, less than 32 bytes (a burst) will

remain in the internal buffer.

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