MPC8280 datasheet(652/1386 Pages) FREESCALE

652 / 1386 page

SDMA Channels and IDMA Emulation

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

19-6

Freescale Semiconductor

•

4-Gbyte maximum block length for each buffer

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32-bit address pointers that can be optionally incremented

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Two buffer handling modes—auto buffer and buffer chaining

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Interrupts are optionally generated for BD transfer completion, external DONE assertion, and

STOP

_IDMA command completion.

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Any channel is independently configurable for data transfer from any 60x, local bus, or PCI source

to any 60x, local bus, or PCI destination

•

Programmable byte-order conversion is supported independently for each DMA channel

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Supports programmable 60x-bus bandwidth usage for system performance optimization

Peripheral to/from memory features include the following:

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External DREQ, DACK, and DONE signals for each channel simplifies the peripheral interface for

memory-to/from-peripheral transfers

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Supports 1-, 2-, 4-, and 8-byte peripheral port sizes

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Supports standard 60x burst accesses (four consecutive 64-bit data phases) to/from peripherals

19.5

IDMA Transfers

The IDMA channel transfers data from a source to a destination using an intermediate transfer buffer (of

programmable size) in the dual-port RAM (note that the IDMA cannot burst to or from the dual-port

RAM). An efficient data-packing algorithm bursts data through the IDMA transfer buffer to minimize the

bus cycles needed for the transfer; however, the IDMA will burst when it has 0x10 or more bytes to

transfer. In single-address peripheral transfers, however, data is transferred directly between memory and

a peripheral device without using the IDMA transfer buffer.

Unaligned data is transferred in single accesses until alignment is achieved. Then, burst transactions are

used (if allowed by the user) to transfer the bulk of the data buffer. Single accesses are used again for any

remaining non-burstable data at the end of the transfer.

19.5.1

Memory-to-Memory Transfers

For memory-to-memory transfers, the IDMA first fills the IDMA transfer buffer in the dual-port RAM by

initiating read accesses on the source bus. It then empties the data from the internal transfer buffer to the

destination bus by initiating write accesses. The transfer sizes for the source and destination buses are

programmed in the IDMA parameter RAM.

For the DMA to generate bursts on the 60x bus, the address boundaries of each burst transfer must be

32-byte aligned. If the transfer does not start on a burst boundary, the IDMA controller transfers the

end-of-burst (EOB) data (1–31 bytes) in non-burst transactions on the source bus and on the destination

bus until reaching the next boundary. When alignment is achieved, subsequent data is bursted until the

remainder of the data in the buffer is less than a burst size (32 bytes). The remaining data is transferred

using non-burst transactions.

MPC8280 Datasheet(PDF) 652 Page - Freescale Semiconductor, Inc

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