MPC8280 datasheet(648/1386 Pages) FREESCALE

648 / 1386 page

SDMA Channels and IDMA Emulation

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

19-2

Freescale Semiconductor

The SDMA channel can be assigned big-endian (Freescale) or little-endian format for accessing buffer

data. These features are programmed in the receive and transmit registers associated with the FCCs,

MCCs, SCCs, SMCs, SPI, and I2C.

If a 60x or local bus error occurs on a CP-related access by the SDMA, the CP generates a unique interrupt

in the SDMA status register (SDSR). The interrupt service routine then reads the appropriate DMA

transfer error address register (PDTEA for the 60x bus or LDTEA for the local bus) to determine the

address the bus error occurred on. The channel that caused the bus error is determined by reading the

channel number from PDTEM or LDTEM. If an SDMA bus error occurs on a CP-related transaction, all

CPM activity stops and the entire CPM must be reset in the CP command register (CPCR). See

Section 19.2, “SDMA Registers.”

19.1

SDMA Bus Arbitration and Bus Transfers

On the MPC8280, the core, PCI bridge, and SDMA can become external bus masters. (The relative priority

of these masters is programmed by the user; see Section 4.3.2, “System Configuration and Protection

Registers,” for programming bus arbitration.)Therefore, any SDMA channel can arbitrate for the bus

against the other internal devices and any external devices present. Once an SDMA channel becomes

system bus master, it remains bus master for one transaction (which can be a byte, half word, word, burst,

or extended special burst) before releasing the bus. This feature, in combination with the zero-clock

arbitration overhead provided by the 60x bus, increases bus efficiency and lowers bus latency.

To minimize the latency associated with slower, character-oriented protocols, an SDMA writes each

character to memory as it arrives without waiting for the next character, and always reads using 16-bit

half-word transfers.

The SDMA can access the 60x bus either at the regular 60x transactions (single-beat accesses, four-beat

bursts) or special two- and three-beat burst accesses. For a further description of this feature see

Section 8.4.3.8, “Extended Transfer Mode.”

A transfer may take multiple bus transactions if the memory provides a less than 64-bit 60x port size or

less than 32-bit local bus port size. An SDMA uses back-to-back bus transactions for the entire

transfer—4-word bursts, 64-bit reads, and 8-, 16-, 32-, or 64-bit writes—before relinquishing the bus. For

example, a 64-bit word 60x-bus read from a 32-bit memory takes two consecutive SDMA bus transactions.

An SDMA can steal transactions with no arbitration overhead when the MPC8280 is bus master.

Figure 19-2 shows an SDMA stealing a transaction from an internal bus master.

MPC8280 Datasheet(PDF) 648 Page - Freescale Semiconductor, Inc