MPC8280 datasheet(681/1386 Pages) FREESCALE

681 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

20-1

Chapter 20

Serial Communications Controllers (SCCs)

The MPC8280 has four serial communications controllers (SCCs), which can be configured independently

to implement different protocols for bridging functions, routers, and gateways, and to interface with a wide

variety of standard WANs, LANs, and proprietary networks. An SCC has many physical interface options

such as interfacing to TDM buses, ISDN buses, and standard modem interfaces.

The SCCs are independent from the physical interface, but SCC logic formats and manipulates data from

the physical interface. Furthermore, the choice of protocol is independent from the choice of interface. An

SCC is described in terms of the protocol it runs. When an SCC is programmed to a certain protocol or

mode, it implements functionality that corresponds to parts of the protocol’s link layer (layer 2 of the OSI

reference model). Many SCC functions are common to protocols of the following controllers:

•

UART, described in Chapter 21, “SCC UART Mode.”

•

HDLC and HDLC bus, described in Chapter 22, “SCC HDLC Mode.”

•

AppleTalk/LocalTalk, described in Chapter 26, “SCC AppleTalk Mode.”

•

BISYNC, described in Chapter 23, “SCC BISYNC Mode.”

•

Transparent, described in Chapter 24, “SCC Transparent Mode.”

•

Ethernet, described in Chapter 25, “SCC Ethernet Mode.”

Although the selected protocol usually applies both to the SCC transmitter and receiver, one half of an SCC

can run transparent operations while the other runs a standard protocol (except Ethernet).

Each Rx and Tx internal clock can be programmed with either an external or internal source. Internal

clocks originate from one of eight baud rate generators (BRGs) or an external clock pin; see Section 16.3,

“NMSI Configuration,” for each SCC’s available clock sources. These clocks can be as fast as a 1:4 ratio

of the CPM frequency. (For example, an SCC internal clock can run at 12.5 MHz in a 50-MHz system.)

However, an SCC’s ability to support a sustained bit stream depends on the protocol as well as other

factors.

Associated with each SCC is a digital phase-locked loop (DPLL) for external clock recovery, which

supports NRZ, NRZI, FM0, FM1, Manchester, and Differential Manchester. If the clock recovery function

is not required (that is, synchronous communication), then the DPLL can be disabled, in which case only

NRZ and NRZI are supported.

An SCC can be connected to its own set of pins on the MPC8280. This configuration is called the

non-multiplexed serial interface (NMSI) and is described in Chapter 15, “Serial Interface with Time-Slot

Assigner.” Using NMSI, an SCC can support standard modem interface signals, RTS, CTS, and CD. If

required, software and additional parallel I/O lines can be used to support additional handshake signals.

Figure 20-1 shows the SCC block diagram.

MPC8280 Datasheet(PDF) 681 Page - Freescale Semiconductor, Inc

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