MPC8280 datasheet(679/1386 Pages) FREESCALE

679 / 1386 page

SDMA Channels and IDMA Emulation

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

19-33

87FE=0x0100

IDMA1_BASE points to 0x0100 where the parameter table base address is located for

IDMA1.

CPCR=0x1e810009

IDMA_start command. IDMA1 page-00111 SBC-10100 op-1001 FLG=1. This write starts

the channel operation.

DMA operation:

START

_IDMA: Initialize all parameter RAM values, start transferring data immediately from the first BD. Data is read from

PCI bus in single burst of (32 aligment + 2016) bytes long, to fill internal buffer.The first write transfer to the 60x bus is

(32 aligment + 6 or 7 burst) bytes long. The rest 8 write transfers are 7 burst long each.

Steady state: Internal buffer is filled in large burst from PCI (STS long). Data is transferred to the 60x bus in 9 transfers

of 7 burst long (DTS) each. Addresses are incremented constantly. Operation continues until the last BD is completed

or STOP_IDMA command is issued. When the last valid BD is complete BC interrupt is set to the core, and IDMA1

channel is stopped, until START_IDMA command is issued.

STOP

_IDMA: after all data in internal buffer is written to the 60x bus, BD is closed and SC interrupt is set. Channel is

stopped until START_IDMA command is issued.

Table 19-17. Programming Example: Memory-to-Memory (PCI-to-60x)—IDMA1 (continued)

Important Init Values

Description

MPC8280 Datasheet(PDF) 679 Page - Freescale Semiconductor, Inc