MPC8280 datasheet(678/1386 Pages) FREESCALE

678 / 1386 page

SDMA Channels and IDMA Emulation

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

19-32

Freescale Semiconductor

19.12.3 Memory-to-Memory (PCI Bus to 60x Bus)—IDMA1

In the example in Table 19-17, the IDMA1 channel transfers data from a memory device on the PCI bus

to one on the 60x bus. IDMA1 channel reads from the PCI bus into the internal buffer in one transfer and

writes to the 60x bus in nine consequent transfers of seven bursts each. It does this operation constantly by

using the internal request mode. The internal buffer is set to 2 Kbytes to maximize use of the PCI bus,

which is not too loaded.

The transfers to memory on the 60x bus are shorter, arbitration priority is low, and the internal request

priority of IDMA1 is lowest to prevent other device starvation on the 60x bus, which is loaded.

Table 19-17. Programming Example: Memory-to-Memory (PCI-to-60x)—IDMA1

Important Init Values

Description

DCM[FB] = 0

Not in fly-by mode.

DCM[LP] = 1

Transfers to 60x have low priority; the destination bus is loaded by higher priority devices.

DCM[DMA_WRAP] = 101 The internal buffer is 2,048 bytes long. Transfers from memory on the source bus (PCI) can

be as long as possible (PCI has high arbitration latency and long bursts). Transfers on the

destination side are shorter, as defined in DTS.

DCM[ERM] = 0

IDMA transfers data continuously until a IDMA_STOP command is issued or until the

transfer complete.s DREQ, DONE, and DACK are not connected externally.

DCM[DT] = DC.

Do not care. DONE assertion is not defined in memory-to-memory mode.

DCM[S/D] = 00

Memory-to-memory mode.

DCM[SINC] = 1

The source memory address is incremented after transfers.

DCM[DINC] = 1

The destination memory address is incremented after every transfer.

IBASE=IBDPTR= 0x0030 The current BD pointer is set to the BD ring Base address (aligned 16 -bits[3–0]=0000).

DPR_BUF = 0x0800

Initiated to address aligned to 2048 (bits[10–0] = 000_0000_0000).

SS_MAX = 2016(0x07e0) Initiated to (internal buffer size - 32) equal to STS in this mode.

STS = 2016(0x07e0)

Transfers from memory on PCI are 2016 bytes long on steady state of work.

DTS = 7*32 (0x00e0)

Transfers to memory on 60x are 224 bytes long (7 60x bursts) for steady-state operations.

We have low arbitration priority on the bus (LP = 1) but once we get it we would like to use

it for more that one burst.

every BD[SDTB] = 1

Source memory is on the PCI (multiplexed with local) bus.

every BD[DDTB] = 0

Destination memory is on the 60x bus.

last BD[SDN] = 0

DONE is not asserted on the last transfer from memory on PCI.

last BD[DDN] = 0

DONE is not asserted on the last transfer to memory on the 60x bus.

last BD[L] = 1

IDMA1 is stopped after last BD complete untill START_IDMA command is reissued.

last BD[I]] = 0

IDMA1 set BC interrupt to the core after last BD complete.

IDMR1=0x0f000000

IDMA1 Mask register is programmed to enable all interrupts.

SIMR_L=0x00000800

Interrupt controller is programmed to enable interrupts from IDMA1.

RCCR=0x00200000

IDMA1 configuration: Internal request priority is the lowest.

MPC8280 Datasheet(PDF) 678 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 678 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL