MPC8280 datasheet(676/1386 Pages) FREESCALE

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SDMA Channels and IDMA Emulation

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

19-30

Freescale Semiconductor

19.12.2 Memory-to-Peripheral Fly-By Mode—IDMA3

In the example in Table 19-16, IDMA3 transfers data from a memory device to a 4-byte wide peripheral,

both on the 60x bus. The transfers are made by issuing 4-byte read transactions to the memory and

asserting DACK so the peripheral samples the data from the bus directly. No address is dedicated for the

peripheral, and no internal buffer is defined in this mode. The IDMA3 channel asserts DONE on the last

read transfer of the last BD to notify the peripheral that there is no data left to transfer.

Last BD(SDN) = 1

DONE is asserted on the last transfer from peripheral.

Last BD(DDN) = 0

DONE is not asserted on the last transfer to memory.

Every BD(DL) = k*STS

Data length must be STS modular (divided by STS without residue).

IDMR2 = 0x0300_0000

IDMA2 Mask register is programmed to enable EDN and BC interrupts only.

SIMR_L = 0x0000_0200

Interrupt controller is programmed to enable interrupts from IDMA2.

PDIRC = 0x1000_0000

PPARC = 0x7000_0000

PSORC = 0x3000_0000

PODRC = 0x2000_0000

Parallel I/O registers are programmed to enable:PC[1] = DREQ2; PC[3] = DACK2; PC[2] =

DONE2.

The peripheral signals are to be connected to these lines accordingly.

RCCR = 0x0000_0000

IDMA2 configuration: DREQ is edge low-to-high. DONE is high-to-low. Request priority is

higher than the SCCs.

88FE = 0x0300

IDMA2_BASE points to 0x0300 where the parameter table base address is located for

IDMA2.

CPCR = 0x22A1_0009

START

_IDMA command. IDMA2 page-01000 SBC-10101 op-1001 FLG=1.This write starts

the channel operation.

DMA operation description:

START

_IDMA: Initialize all parameter RAM values, wait for DREQ to open the first BD. The four first DREQs trigger

single, 8-byte read transactions from the peripheral until data in the internal buffer is 32 bytes long. Then, a write

transaction to memory is done with the size needed for alignment.

Steady state: Every DREQ assertion triggers a read transaction of 8 bytes from the peripheral. If the data in the internal

buffer is more than 31 bytes a write transaction to memory of 32 bytes (one local burst) follows immediately. Memory

address is incremented constantly. Last read transaction of the last BD from the peripheral is combined with DONE

assertion.

STOP

_IDMA: After all data in internal buffer is written to memory in one transfer, SC bit is set in IDSR (SC interrupt to

the core is not enabled) and BD is closed. Channel is stopped until START_IDMA command is reissued.

DONE assertion by the peripheral: All data in internal buffer is written to memory in one transfer. At the end of the

transfer, EDN interrupt is set to host. Additional DREQ assertions are ignored. IDMA2 channel is stopped until

START

_IDMA command is issued.

Table 19-16. Example: Memory-to-Peripheral Fly-By Mode (on 60x)–IDMA3

Important Init Values

Description

DCM[FB] = 1

Fly-by mode.

DCM[LP] = x

Don’t care. Transfer from memory to peripheral on the 60x bus is high priority.

DCM[DMA_WRAP] = DC Don’t care. No internal buffer is used.

Table 19-15. Example: Peripheral-to-Memory Mode—IDMA2 (continued)

Important Init Values

Description

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