MPC8280 datasheet(672/1386 Pages) FREESCALE

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SDMA Channels and IDMA Emulation

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

19-26

Freescale Semiconductor

19.9

IDMA Commands

The user has two commands to control each IDMA channel. These commands are executed through the

CP command register (CPCR); see Section 14.4, “Command Set.”

19.9.1

START

_IDMA Command

The START_IDMA command is used to start a transfer on an IDMA channel. The user must initialize all

parameters relevant for the correct operation of the channel (IDMAx_BASE and IDMA channel parameter

table) before issuing this command.

To restart the channel operation, the START_IDMA command can be reissued after every pause in channel

activity. The user must ensure that parameters are correct for the channel to continue operation correctly.

The parameter ISTATE of the IDMA parameter RAM should be cleared before every issue of a

START

_IDMA command.

An IDMA pause may occur for one of the following reasons:

•

The channel is out of buffers—IDSR[OB] event is set and an interrupt is generated to the core, if

enabled.

•

DONE was asserted externally and DCM[DT] = 0 (see Table 19-5.). An IDSR[EDN] event is set

and an interrupt is generated to the core, if enabled.

•

STOP

_IDMA command was issued.

•

The channel has finished a transfer of a BD with the last bit (L) set.

If the START_IDMA command is reissued and channel has more buffers to transfer, it restarts transferring

data according to the next BD in the buffer table.

In external request mode (ERM=1), the START_IDMA command initializes the channel, but the first data

transfer is performed after external DREQx assertion.

In internal request mode (ERM=0), the START_IDMA command starts the data transfer almost immediately,

with a delay which depends on the CP load.

19.9.2

STOP

_IDMA Command

The STOP_IDMA command is issued to stop the transfer of an IDMA channel.

0x08

0–31

Source

Buffer

Pointer

Holds the address of the associated buffer. Buffers may reside in internal or external

memory. Note that if the source/destination is a device, the pointer should contain the

device address.

In fly-by mode, the pointers should contain the memory address.

0x0C

0–31

Destination

Buffer

Pointer

Table 19-10. IDMA BD Field Descriptions (continued)

Offset

Bits

Name

Description

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