MPC8280 datasheet(668/1386 Pages) FREESCALE

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SDMA Channels and IDMA Emulation

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

19-22

Freescale Semiconductor

19.8.3

IDMA Performance

The transfer parameters STS, DTS, SS_MAX, and DMA_WRAP determine the amount of data transferred

for each START_IDMA command issued. Using large internal IDMA transfer buffers and the maximum

transfer sizes allows longer transfers to memory devices, optimizes bus usage and thus reduces the overall

load on the CP.

For example, 2,016 bytes can be transferred by issuing one START_IDMA command using a 2-Kbyte

internal transfer buffer, or by issuing 63 START_IDMA commands using a 64-byte buffer. The load on the

CP in the second case is about 63 times more than the first.

19.8.4

IDMA Event Register (IDSR) and Mask Register (IDMR)

The IDMA event (status) register (IDSR) is used to report events recognized by the IDMA controller. On

recognition of an event, the controller sets the corresponding IDSR bit. Each IDMA event bit can generate

a maskable interrupt to the core. Even bits are cleared by writing ones; writing zeros has no effect.

The IDMA mask register (IDMR) has the same format as IDSR. Setting IDMR bits enables, and clearing

IDMR bits disables, the corresponding interrupts in the event register.

011

512

15 * 32

1, 2, 4, 8 (single); 32

(burst)

1, 2, 4, 8 (single); 32

(burst)

15 * 32

100

1024

31 * 32

1, 2, 4, 8 (single); 32

(burst)

1, 2, 4, 8 (single); 32

(burst)

31 * 32

101

2048

63 * 32

1, 2, 4, 8 (single); 32

(burst)

1, 2, 4, 8 (single); 32

(burst)

63 * 32

1These values come out as a single transaction on the bus.

2Peripherals that can accept bursts of 32 bytes are supported.

Table 19-8. Valid STS/DTS Values for Peripherals (continued)

DMA_WRAP

Internal Buffer Size SS_MAX

S/D Mode

STS (in Bytes)

DTS (in Bytes)

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