MPC8280 datasheet(664/1386 Pages) FREESCALE

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SDMA Channels and IDMA Emulation

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

19-18

Freescale Semiconductor

19.8.2.1

DMA Channel Mode (DCM)

The IDMA channel mode (DCM), shown in Figure 19-8, is a 16-bit field within the IDMA parameter

RAM, that controls the operation modes of the IDMA channel. As are all other IDMA parameters, the

DCM is undefined at reset.

Table 19-5 describes DCM bits.

Field

—

TC2

—

DMA_WRAP

SINC DINC ERM

S/D

Reset

—

R/W

Figure 19-8. DCM Parameters

Table 19-5. DCM Field Descriptions

Bits

Name

Description

Fly-by mode. See Table 19-6.

0 Dual-address mode.

1 Fly-by (single-address) mode. The internal IDMA transfer buffer is not used. Valid only in

peripheral-to-memory (S/D=10) or memory-to-peripheral (S/D=01) modes.

Low priority. Applies to memory-to-memory accesses only. See Section 4.3.2, “System

Configuration and Protection Registers.”

0 The IDMA transaction to memory is in middle CPM request priority.

1 The IDMA transaction to memory is in low CPM request priority.

Note that IDMA single-address (fly-by) transfers with external peripherals are always high

priority, ignoring this bit and bypassing other pending SDMA requests.

2–4

—

Reserved, should be cleared.

TC2

Driven on TC[2] during IDMA transactions. The TC[0–1] signals are always driven to 0b11

during IDMA transactions.

—

Reserved, should be cleared.

7–9

DMA_WRAP

DMA wrap. Defines the size of the IDMA transfer buffer. The IDMA pointer wraps to the

beginning of the buffer whenever DMA_WRAP bytes have been transferred to/from the buffer.

000 64 byte

001 128 byte

010 256 byte

011 512 byte

100 1024 byte

101 2048 byte

11x Reserved

Table 19-7 and Table 19-8 describes the relations between the parameter’s initial value and

SS_MAX, STS, DTD and DCM[S/D] parameters.

The IDMA transfer buffer (DPR_BUF) size should be consistent with DCM[DMA_WRAP]; that is

DPR_BUF = 64 X 2(DMA_WRAP).

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