MPC8280 datasheet(661/1386 Pages) FREESCALE

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SDMA Channels and IDMA Emulation

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

19-15

operation. In addition the core initializes the parallel I/O registers to enable IDMA external signals,

if needed, and other registers related to the channel priority and operation modes; see

Section 19.11, “Programming the Parallel I/O Registers.” The core initiates the IDMA BDs to

point to the data for the transfer and/or a free space for data to be transferred to, and starts the

transfer by issuing the START_IDMA command.

•

During data transfer, the IDMA accepts requests for data transfers and provides addressing and bus

control for the transfers.

•

Termination occurs when the IDMA operation completes or the peripheral asserts DONE

externally. The core can initiate termination by using the STOP_IDMA command. The IDMA can

interrupt the core if interrupts are enabled to signal for operation termination and other events

related to the data transfer.

The IDMA uses a data structure, which, as with serial controller BDs, allows flexible data allocation and

eliminates the need for core intervention between transfers. BDs contain information describing the data

block and special control options for the DMA operation while transferring the data block.

19.8.1

Auto Buffer and Buffer Chaining

The core processor should initialize the IDMA BD table with the appropriate buffer handling mode, source

address, destination address, and block length. See Figure 19-7.

Figure 19-7. IDMA

x Channel BD Table

Data associated with each IDMA channel is stored in buffers and each buffer is referenced by a BD that

uses a circular table structure in the dual-port RAM. Control options such as interrupt and DONE assertion

are also programmed on a per-buffer basis in each BD.

IDMAx BD Base

Address (IBASE)

Source Device or

Buffer 0

Source Device or

Buffer 1

Source Device or

Buffer 2

Source Device or

Buffer n

BD 0

Destination Device or

Buffer 0

BD 1

BD 2

BD n

Destination Device or

Buffer 1

Destination Device or

Buffer 2

Destination Device or

Buffer n

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