MPC8280 datasheet(662/1386 Pages) FREESCALE

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SDMA Channels and IDMA Emulation

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

19-16

Freescale Semiconductor

Data may be transferred in the two following modes:

•

Auto buffer mode. The IDMA continuously transfers data to/from the location programmed in the

BD until a STOP_IDMA command is issued or DONE is asserted externally.

•

Buffer chaining mode. Data is transferred according to the first BD parameters, then the second BD

and so forth. The first BD is reused (if ready) until the BD with the last bit set is reached. IDMA

transfers stop and restarts when the BD table is reinitialized and a START_IDMA command is issued.

19.8.2

IDMA

x Parameter RAM

When an IDMAx channel is configured to auto buffer or buffer chaining mode, the MPC8280 uses the

IDMAx parameters listed in the Table 19-4. Parameters should be modified only while the channel is

disabled, that is, before the first START_IDMA command or when the event register’s stop-completed bit

(IDSR[SC]) is set following a STOP_IDMA command.

Each IDMAx channel parameter table can be placed at any 64-byte aligned address in the dual-port RAM’s

general-purpose area (banks 1–8, 11 and 12). The CP accesses each IDMAx channel parameter table using

a user-programmed pointer (IDMAx_BASE) located in the parameter RAM; see Section 14.5.2,

“Parameter RAM.” For example, if the IDMA1 channel parameter table is to be placed at address offset

0x2000 in the dual-port RAM, write 0x2000 to IDMA1_BASE.

Table 19-4. IDMA

x Parameter RAM

Offset 1

Name

Width

Description

0x00

IBASE

Hword IDMA BD table base address. Defines the starting location in the dual-port RAM

for the set of IDMA BDs. It is an offset from the beginning of the dual-port RAM.

The user must initialize IBASE before enabling the IDMA channel and should not

overlap BD tables of two enabled serial controllers or IDMA channels or erratic

operation results. IBASE should be 16-byte aligned.

0x02

DCM

Hword DMA channel mode. See Section 19.8.2.1, “DMA Channel Mode (DCM).”

0x04

IBDPTR

Hword IDMA BD pointer. Points to the current BD during transfer processing. Points to

the next BD to be processed when an idle channel is restarted. Initialize to

IBASE before the first START_IDMA command. If BD[W] = 1, the CP initializes

IBPTR to IBASE When the end of an IDMA BD table is reached. After a

STOP

_IDMA command is issued, IBDPTR points to the next BD to be processed.

It can be modified after SC interrupt is set and before a START_IDMA command

is reissued.

0x06

DPR_BUF

Hword IDMA transfer buffer base address. The base address should be aligned

according to the buffer size determined by DCM[DMA_WRAP]. The transfer

buffer size should be consistent with DCM[DMA_WRAP]; that is, DPR_BUF =

(64 X 2DMA_WRAP). See Section 19.8.2.1, “DMA Channel Mode (DCM).”

0x08

BUF_INV

Hword Internal buffer inventory. Indicates the quantity of data inside the internal buffer.

0x0A

SS_MAX

Hword Steady-state maximum transfer size in bytes. User-defined parameter to

increase microcode efficiency. Initialize to internal_buffer_size - 32, that is,

SS_MAX = (64 X 2DMA_WRAP) - 32. If possible, SS_MAX is used as the transfer

size on transfers to/from memory in memory-to-peripheral mode or in

peripheral-to-memory mode. For memory-to-memory mode, SS_MAX is used

as the transfer size for at least one of the devices. SS_MAX should be consistent

with STS, DTS, and DCM[S/D]. See Table 19-7 and Table 19-8.

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