MPC8280 datasheet(665/1386 Pages) FREESCALE

665 / 1386 page

SDMA Channels and IDMA Emulation

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

19-19

SINC

Source increment address.

0 Source address pointer (S_PTR) is not incremented in the source read transaction. Should

be cleared for peripheral-to-memory transfers if the peripheral has a fixed address.

1 CP increments the source address pointer (S_PTR) with the number of bytes transferred in

the source read transaction. Used for memory-to-memory and memory-to-peripheral

transfers.

In fly-by mode, SINC controls the memory address increment and should equal DINC.

DINC

Destination increment address.

0 Destination address pointer (D_PTR) is not changed in the destination write transaction.

Used for memory-to-peripheral transfers if the peripheral has a fixed address.

1 CP increments the destination pointer (D_PTR) with the number of bytes transferred in the

destination write transaction. Used for memory-to-memory and memory-to-peripheral

transfers.

In fly-by mode, DINC should equal SINC.

ERM

External request mode.

0 The CP transfers continuously, as if an external level request is asserted, regardless of the

DREQ signal assertion. The CP stops the transfer when there are no more valid BDs or after

a STOP_IDMA command is issued. DONE assertion by a external device is ignored.

1 The CP responds to DREQ as configured (edge/level) by performing single- or dual-address

transfers. The CP also responds to DONE assertions.

Note: Memory-to-memory transfers (S/D=00) with external request (ERM=1) is allowed, but

DONE assertion is not supported in this mode (DONE should be disabled).

DONE treatment:

0 After external DONE assertion, the IDMA ignores further DREQ assertions. The CP closes

the current BD and IDMA stops. START_IDMA command should be issued before assertion of

another DREQ.

1 After external DONE assertion, the CP closes the current BD. The IDMA continues to the

next BD when DREQ is asserted.

14–1

S/D

Source/destination is a peripheral device or memory. See Table 19-6..

00 Read from memory, write to memory.

10 Read from peripheral, write to memory.

01 Read from memory, write to peripheral.

11 Reserved

When a device is a peripheral:

•DACK is asserted during transfers to/from it.

• It may assert DONE to terminate all accesses to/from it.

• It can be operated in fly-by mode—respond to DACK ignoring the address.

• It gets highest DMA priority on the bus arbiter and the lowest DMA latency available.

Table 19-5. DCM Field Descriptions (continued)

Bits

Name

Description

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