MPC8280 datasheet(669/1386 Pages) FREESCALE

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SDMA Channels and IDMA Emulation

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

19-23

Figure 19-9 shows the bit format for IDSR and IDMR.

Table 19-9 describes IDSR/IDMR fields.

19.8.5

IDMA BDs

Source addresses, destination addresses, and byte counts are presented to the CP using the special IDMA

BDs. The CP reads the BDs, programs the SDMA channel, and notifies the core about the completion of

a buffer transfer using the IDMA BDs. This concept is similar to the one used for the serial controllers on

the MPC8280 except that the BD is larger because it contains additional information.

34567

Field

—

EDN

Reset

0000_0000

R/W

Addr

0x11020 (IDSR1), 0x11028 (IDSR2), 0x11030 (IDSR3), 0x11038 (IDSR4)/

0x11024 (IDMR1), 0x1102C (IDMR2), 0x11034 (IDMR3), 0x1103C (IDMR4)

Figure 19-9. IDMA Event/Mask Registers (IDSR/IDMR)

Table 19-9. IDSR/IDMR Field Descriptions

Bits

Name

Description

0–3

—

Reserved, should be cleared.

Stop completed. Set after the IDMA channel completes processing the STOP_IDMA command. Do

not change channel parameters until SC is set.

Out of buffers. Set to indicate that the IDMA channel encountered no valid BDs for the transfer.

EDN

External DONE was asserted by device. Set to indicate that the IDMA channel terminated a transfer

because DONE was asserted by an external device, on the former SDMA transaction.

BD completed. Set only after all data of a BD whose I (interrupt) bit is set has completed transfer to

the destination.

Offset + 0

—

SDN DDN DGBL

DBO

—

DDTB

Offset + 2

—

SGBL

SBO

—

SDTB

—

Offset + 4

Data Length

Offset + 6

Offset + 8

Source Data Buffer Pointer

Offset + A

Offset + C

Destination Data Buffer Pointer

Offset + E

Figure 19-10. IDMA BD Structure

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