MPC8280 datasheet(671/1386 Pages) FREESCALE

671 / 1386 page

SDMA Channels and IDMA Emulation

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

19-25

DDN

Destination done

0DONE is inactive during this BD.

1 The IDMA asserts DONE at the last write data phase of the BD.

In fly-by mode (DCM[FB] = 1), DDN should be same as SDN.

DGBL

Destination global

0 Snooping is not activated.

1 Snooping is activated for write transactions to the destination.

In fly-by mode, should be the same as SGBL.

12-13

DBO

Destination byte ordering:

01 Munged little Endian.

1x Big endian (Freescale).

00 Reserved

In fly-by mode, should be the same as SBO.

—

Reserved, should be cleared.

DDTB

Destination data bus.

0 The destination address lies within the 60x bus.

1 The destination address lies within the local bus.

In fly-by mode, should be the same as SDTB.

0x02

0-1

—

Reserved, should be cleared.

SGBL

Source global

0 Snooping is not activated.

1 Snooping is activated for read transactions from the source.

In fly-by mode, should be the same as DGBL.

3-4

SBO

Source byte ordering:

01 Munged little endian

1x Big endian (Freescale)

00 Reserved

In fly-by mode, should be the same as DBO.

—

Reserved, should be cleared.

SDTB

Source data bus.

0 The source address lies within the 60x bus.

1 The source address lies within the local or PCI buses.

In fly-by mode, should be the same as DDTB.

7-15

—

Reserved, should be cleared.

0x04

0–31

Data

Length

Number of bytes the IDMA transfers. Should be programmed to a value greater than

zero.

Note: When operating with a peripheral that accepts only single bus transactions

(transfer size < 32), data length should be a multiple of the peripheral transfer size

(STS for S/D = 10, or DTS for S/D = 01). Also, there is no error notification if the

data length does not match the buffer sizes.

Table 19-10. IDMA BD Field Descriptions (continued)

Offset

Bits

Name

Description

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