MPC8280 datasheet(689/1386 Pages) FREESCALE

689 / 1386 page

Serial Communications Controllers (SCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

20-9

20.1.2

Protocol-Specific Mode Register (PSMR)

The protocol implemented by an SCC is selected by its GSMR_L[MODE]. Each SCC has an additional

protocol-specific mode register (PSMR) that configures it specifically for the chosen protocol. The PSMR

fields are described in the specific chapters that describe each protocol. PSMRs are cleared at reset.

PSMRs reside at the following addresses: 0x11A08 (PSMR1), 0x11A28 (PSMR2), 0x11A48 (PSMR3),

and 0x11A68 (PSMR4).

20.1.3

Data Synchronization Register (DSR)

Each SCC has a data synchronization register (DSR) that specifies the pattern used for frame

synchronization. The programmed value for DSR depends on the protocol:

•

UART—DSR is used to configure fractional stop bit transmission.

•

BISYNC and transparent—DSR should be programmed with the sync pattern.

•

Ethernet—DSR should be programmed with 0xD555.

•

HDLC—At reset, DSR defaults to 0x7E7E (two HDLC flags), so it does not need to be written.

Figure 20-4 shows the sync fields.

28–31

MODE Channel protocol mode. See also GSMR_H[TTX, TRX].

0000 HDLC

0001 Reserved

0010 AppleTalk/LocalTalk

0011 SS7—reserved for RAM microcode

0100 UART

0101 Profibus—reserved for RAM microcode

0110 Reserved

0111 Reserved

1000 BISYNC

1001 Reserved

101x Reserved

1100 Ethernet

11xx Reserved

Field

SYN2

SYN1

Reset

0111_1110

R/W

Addr

0x11A0E (DSR1); 0x11A2E (DSR2); 0x11A4E (DSR3); 0x11A6E (DSR4)

Figure 20-4. Data Synchronization Register (DSR)

Table 20-2. GSMR_L Field Descriptions (continued)

Bit

Name

Description

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