MPC8280 datasheet(696/1386 Pages) FREESCALE

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Serial Communications Controllers (SCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

20-16

Freescale Semiconductor

20.3.3

Handling SCC Interrupts

To allow interrupt handling for SCC-specific events, event, mask, and status registers are provided within

each SCC’s internal memory map area; see Table 20-7. Because interrupt events are protocol-dependent,

event descriptions are found in the specific protocol chapters.

Follow these steps to handle an SCC interrupt:

1. When an interrupt occurs, read SCCE to determine the interrupt sources and clear those SCCE bits

(in most cases).

2. Process the TxBDs to reuse them if SCCE[TX] or SCCE[TXE] = 1. If the transmit speed is fast or

the interrupt delay is long, the SCC may have sent more than one Tx buffer. Thus, it is important

to check more than one TxBD during interrupt handling. A common practice is to process all

TxBDs in the handler until one is found with its R bit set.

3. Extract data from the RxBD if SCCE[RX], SCCE[RXB], or SCCE[RXF] is set. As with transmit

buffers, if the receive speed is fast or the interrupt delay is long, the SCC may have received more

than one buffer and the handler should check more than one RxBD. A common practice is to

process all RxBDs in the interrupt handler until one is found with RxBD[E] set.

4. Execute the rfi instruction.

Additional information about interrupt handling can be found in Section 4.2, “Interrupt Controller.”

20.3.4

Initializing the SCCs

The SCCs require that a number of registers and parameters be configured after a power-on reset.

Regardless of the protocol used, follow these steps to initialize SCCs:

1. Write the parallel I/O ports to configure and connect the I/O pins to the SCCs.

2. Configure the parallel I/O registers to enable RTS, CTS, and CD if these signals are required.

Table 20-7. SCC

x Event, Mask, and Status Registers

IMMR Offset

Description

SCCE

0x11A10 (SCCE1);

0x11A30 (SCCE2);

0x11A50 (SCCE3);

0x11A70 (SCCE4)

SCC event register. This 16-bit register reports events recognized by any of the SCCs. When an

event is recognized, the SCC sets its corresponding bit in SCCE, regardless of the

corresponding mask bit. When the corresponding event occurs, an interrupt is signaled to the

SIVEC register. Bits are cleared by writing ones (writing zeros has no effect). SCCE is cleared

at reset and can be read at any time.

SCCM

0x11A14 (SCCM1);

0x11A34 (SCCM2);

0x11A54 (SCCM3);

0x11A74 (SCCM4)

SCC mask register. The 16-bit, read/write register allows interrupts to be enabled or disabled

using the CPM for specific events in each SCC channel. An interrupt is generated only if SCC

interrupts in this channel are enabled in the SIU interrupt mask register (SIMR). If an SCCM bit

is zero, the CPM does not proceed with interrupt handling when that event occurs. The SCCM

and SCCE bit positions are identical.

SCCS

0x11A17 (SCCS1);

0x11A37 (SCCS2);

0x11A57 (SCCS3);

0x11A77 (SCCS4)

SCC status register. This 8-bit, read-only register allows monitoring of the real-time status of

RXD.

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