MPC8280 datasheet(719/1386 Pages) FREESCALE

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SCC UART Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

21-13

21.16 UART Mode Register (PSMR)

For UART mode, the SCC protocol-specific mode register (PSMR) is called the UART mode register.

Many bits can be modified while the receiver and transmitter are enabled. Figure 21-6 shows the PSMR

in UART mode.

Table 21-9 describes PSMR UART fields.

Framing

The UART reports a framing errors when it receives a character with no stop bit, regardless of the

mode. The channel writes the received character to the buffer, closes it, sets RxBD[FR], generates the

RX interrupt if not masked, increments FRMEC, but does not check parity for this character. In

automatic multidrop mode, the receiver immediately enters hunt mode. If the UART allows data with

no stop bits (PSMR[RZS] = 1) when in synchronous mode (PSMR[SYN] = 1), framing errors are

reported but reception continues assuming the unexpected zero is the start bit of the next character;

in this case, the user may ignore a reported framing error until multiple framing errors occur within a

short period.

Break

Sequence

When the first break sequence is received, the UART increments the break error counter BRKEC. It

updates BRKLN when the sequence completes. After the first 1 is received, the UART sets

SCCE[BRKE], which generates an interrupt if not masked. If the UART is receiving characters when it

receives a break, it closes the Rx buffer, sets RxBD[BR], and sets SCCE[RX], which can generate an

interrupt if not masked. If PSMR[RZS] = 1 when the UART is in synchronous mode, a break sequence

is detected after two successive break characters are received.

Field FLC

FRZ

RZS

SYN

DRT

—

PEN

RPM

TPM

Reset

R/W

Addr

0x11A08 (PSMR1); 0x11A28 (PSMR2); 0x11A48 (PSMR3); 0x11A68 (PSMR4)

Figure 21-6. Protocol-Specific Mode Register for UART (PSMR)

Table 21-9. PSMR UART Field Descriptions

Bit

Name

Description

FLC

Flow control.

0 Normal operation. The GSMR and port C registers determine the mode of CTS.

1 Asynchronous flow control. When CTS is negated, the transmitter stops at the end of the current

character. If CTS is negated past the middle of the current character, the next full character is sent

before transmission stops. When CTS is asserted again, transmission continues where it left off

and no CTS lost error is reported. Only idle characters are sent while CTS is negated.

Stop length. Selects the number of stop bits the SCC sends. SL can be modified on-the-fly. The

receiver is always enabled for one stop bit unless the SCC UART is in synchronous mode and

PSMR[RZS] is set. Fractional stop bits are configured in the DSR.

0 One stop bit.

1 Two stop bits.

Table 21-8. Reception Errors (continued)

Error

Description

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