MPC8280 datasheet(715/1386 Pages) FREESCALE

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SCC UART Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

21-9

21.10 Hunt Mode (Receiver)

A UART receiver in hunt mode remains deactivated until an idle or address character is recognized,

depending on PSMR[UM]. A receiver is forced into hunt mode by issuing an ENTER HUNT MODE

command.

The receiver aborts any message in progress when ENTER HUNT MODE is issued. When the message is

finished, the receiver is reenabled by detecting the idle line (one idle character) or by the address bit of the

next message, depending on PSMR[UM]. When a receiver in hunt mode receives a break sequence, it

increments BRKEC and generates a BRK interrupt condition.

21.11 Inserting Control Characters into the Transmit Data Stream

The SCC UART transmitter can send out-of-sequence, flow-control characters like XON and XOFF. The

controller polls the transmit out-of-sequence register (TOSEQ), shown in Figure 21-4, whenever the

transmitter is enabled for UART operation, including during a UART freeze operation, UART buffer

transmission, and when no buffer is ready for transmission. The TOSEQ character (in CHARSEND) is

sent at a higher priority than the other characters in the transmit buffer, but does not preempt characters

already in the transmit FIFO. This means that the XON or XOFF character may not be sent for eight or

four (SCC) character times. To reduce this latency, set GSMR_H[TFL] to decrease the FIFO size to one

character before enabling the transmitter.

0x60

0–1

0b11

Must be set. Used to mark the end of the control character table in case eight

characters are used. Setting these bits ensures correct operation during control

character recognition.

2–7

—

Reserved

8–15

RCCM

Received control character mask. Used to mask the comparison of

CHARACTER

n. Each RCCM bit corresponds to the respective bit of

CHARACTER

n and decodes as follows.

0 Ignore this bit when comparing the incoming character to CHARACTER

1 Use this bit when comparing the incoming character to CHARACTER

0x62

0–7

—

Reserved

8–15

RCCR

Received control character register. If the newly arrived character matches and is

rejected from the buffer (R = 1), the PIP controller writes the character into the

RCCR and generates a maskable interrupt. If the core does not process the

interrupt and read RCCR before a new control character arrives, the previous

control character is overwritten.

Table 21-4. Control Character Table, RCCM, and RCCR Descriptions (continued)

Offset

Bits

Name

Description

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