MPC8280 datasheet(711/1386 Pages) FREESCALE

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SCC UART Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

21-5

21.5

Data-Handling Methods: Character- or Message-Based

An SCC UART controller uses the same BD table and buffer structures as the other protocols and supports

both multibuffer, message-based and single-buffer, character-based operation.

For character-based transfers, each character is sent with stop bits and parity and received into separate

1-byte buffers. A maskable interrupt is generated when each buffer is received.

In a message-based environment, transfers can be made on entire messages rather than on individual

characters. To simplify programming and save processor overhead, a message is transferred as a linked list

of buffers without core intervention. For example, before handling input data, a terminal driver may wait

for an end-of-line character or an idle timeout rather than be interrupted when each character is received.

Conversely, ASCII files can be sent as messages ending with an end-of-line character.

When receiving messages, up to eight control characters can be configured to mark the end of a message

or generate a maskable interrupt without being stored in the buffer. This option is useful when flow control

characters such as XON or XOFF are needed but are not part of the received message. See Section 21.9,

“Receiving Control Characters.”

21.6

Error and Status Reporting

Overrun, parity, noise, and framing errors are reported via the BDs and/or error counters in the UART

parameter RAM. Signal status is indicated in the status register; a maskable interrupt is generated when

status changes.

0x4C

RTEMP

Hword Temp storage

0x60

RCCM

Hword Receive control character mask. Used to mask comparison of CHARACTER1–8

so classes of control characters can be defined. A one enables the comparison,

and a zero masks it.

0x62

RCCR

Hword Receive control character register. Used to hold the last rejected control

character (not written to the Rx buffer). Generates a maskable interrupt. If the

core does not process the interrupt and read RCCR before a new control

character arrives, the previous control character is overwritten.

0x64

RLBC

Hword Receive last break character. Used in synchronous UART when PSMR[RZS] =

1; holds the last break character pattern. By counting zeros in RLBC, the core

can measure break length to a one-bit resolution. Read RLBC by counting the

zeros written from bit 0 to where the first one was written. RLBC =

0b001xxxxxxxxxxxxx indicates two zeros; 0b1xxxxxxxxxxxxxxx indicates no

zeros.

Note that RLBC can be used in combination with BRKLN above to calculate the

number of bits in the break sequence: (BRKLN * character length) + (number of

zeros in RLBC).

1 From SCC base. See Section 20.3.1, “SCC Base Addresses.”

Table 21-1. UART-Specific SCC Parameter RAM Memory Map (continued)

Offset 1

Name

Width

Description

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