MPC8280 datasheet(710/1386 Pages) FREESCALE

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SCC UART Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

21-4

Freescale Semiconductor

Table 21-1. UART-Specific SCC Parameter RAM Memory Map

Offset 1

Name

Width

Description

0x30

—

DWord Reserved

0x38

MAX_IDL

Hword Maximum idle characters. When a character is received, the receiver begins

counting idle characters. If MAX_IDL idle characters are received before the next

data character, an idle timeout occurs and the buffer is closed, generating a

maskable interrupt request to the core to receive the data from the buffer. Thus,

MAX_IDL offers a way to demarcate frames. To disable the feature, clear

MAX_IDL. The bit length of an idle character is calculated as follows: 1 + data

length (5–9) + 1 (if parity is used) + number of stop bits (1–2). For 8 data bits, no

parity, and 1 stop bit, the character length is 10 bits.

0x3A

IDLC

Hword Temporary idle counter. Holds the current idle count for the idle timeout process.

IDLC is a down-counter and does not need to be initialized or accessed.

0x3C

BRKCR

Hword Break count register (transmit). Determines the number of break characters the

transmitter sends. The transmitter sends a break character sequence when a

STOP TRANSMIT

command is issued. For 8 data bits, no parity, 1 stop bit, and

1 start bit, each break character consists of 10 zero bits.

0x3E

PAREC

Hword User-initialized,16-bit (modulo–2

) counters incremented by the CP.

PAREC counts received parity errors.

FRMEC counts received characters with framing errors.

NOSEC counts received characters with noise errors.

BRKEC counts break conditions on the signal. A break condition can last for

hundreds of bit times, yet BRKEC is incremented only once during that period.

0x40

FRMEC

Hword

0x42

NOSEC

Hword

0x44

BRKEC

Hword

0x46

BRKLN

Hword Last received break length. Holds the length of the last received break character

sequence measured in character units. For example, if RXD

x is low for 20 bit

times and the defined character length is 10 bits, BRKLN = 0x002, indicating that

the break sequence is at least 2 characters long. BRKLN is accurate to within

one character length.

0x48

UADDR1

Hword UART address character 1/2. In multidrop mode, the receiver provides automatic

address recognition for two addresses. In this case, program the lower order

bytes of UADDR1 and UADDR2 with the two preferred addresses.

0x4A

UADDR2

Hword

0x4C

RTEMP

Hword Temp storage

0x4E

TOSEQ

Hword Transmit out-of-sequence character. Inserts out-of-sequence characters, such

as XOFF and XON, into the transmit stream. The TOSEQ character is put in the

Tx FIFO without affecting a Tx buffer in progress. See Section 21.11, “Inserting

Control Characters into the Transmit Data Stream.”

0x50

CHARACTER1

Hword Control character 1–8. These characters define the Rx control characters on

which interrupts can be generated.

0x52

CHARACTER2

Hword

0x54

CHARACTER3

Hword

0x56

CHARACTER4

Hword

0x58

CHARACTER5

Hword

0x5A

CHARACTER6

Hword

0x5C

CHARACTER7

Hword

0x5E

CHARACTER8

Hword

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