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MPC8280 Datasheet(PDF) 721 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 721 Page - Freescale Semiconductor, Inc |
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721 / 1386 page ![]() SCC UART Mode MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 21-15 21.17 SCC UART Receive Buffer Descriptor (RxBD) The CPM uses RxBDs to report on each buffer received. The CPM closes the current buffer, generates a maskable interrupt, and starts receiving data into the next buffer after one of the following occurs: • A user-defined control character is received. • An error occurs during message processing. • A full receive buffer is detected. • A MAX_IDL number of consecutive idle characters is received. •An ENTER HUNT MODE or CLOSE RXBD command is issued. • An address character is received in multidrop mode. The address character is written to the next buffer for a software comparison. Figure 21-7 shows an example of how RxBDs are used in receiving. 10 — Reserved, should be cleared. 11 PEN Parity enable. 0No parity. 1 Parity is enabled and determined by the parity mode bits. 12–13, 14–15 RPM, TPM Receiver/transmitter parity mode. Selects the type of parity check the receiver/transmitter performs; can be modified on-the-fly. Receive parity errors can be ignored but not disabled. 00 Odd parity. If a transmitter counts an even number of ones in the data word, it sets the parity bit so an odd number is sent. If a receiver receives an even number, a parity error is reported. 01 Low parity (space parity). A transmitter sends a zero in the parity bit position. If a receiver does not read a 0 in the parity bit, a parity error is reported. 10 Even parity. Like odd parity, the transmitter adjusts the parity bit, as necessary, to ensure that the receiver receives an even number of one bits; otherwise, a parity error is reported. 11 High parity (mark parity). The transmitter sends a one in the parity bit position. If the receiver does not read a 1 in the parity bit, a parity error is reported. Table 21-9. PSMR UART Field Descriptions (continued) Bit Name Description |
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