MPC8280 datasheet(725/1386 Pages) FREESCALE

725 / 1386 page

SCC UART Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

21-19

The data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).”

21.19 SCC UART Event Register (SCCE) and Mask Register (SCCM)

The SCC event register (SCCE) is used to report events recognized by the UART channel and to generate

interrupts. When an event is recognized, the controller sets the corresponding SCCE bit. Interrupts can be

masked in the UART mask register (SCCM), which has the same format as SCCE. Setting a mask bit

enables the corresponding SCCE interrupt; clearing a bit masks it. Figure 21-10 shows example interrupts

that can be generated by the SCC UART controller.

Interrupt.

0 No interrupt is generated after this buffer is processed.

1 SCCE[TX] is set after this buffer is processed by the CPM, which can cause an interrupt.

Clear-to-send report.

0 The next buffer is sent with no delay (assuming it is ready), but if a CTS lost condition occurs,

TxBD[CT] may not be set in the correct TxBD or may not be set at all. Asynchronous flow control,

however, continues to function normally.

1Normal CTS lost error reporting and three bits of idle are sent between consecutive buffers.

Address. Valid only in multidrop mode—automatic or manual.

0 This buffer contains only data.

1 This buffer contains address characters. All data in this buffer is sent as address characters.

Continuous mode.

0 Normal operation. The CPM clears R after this BD is closed.

1 The CPM does not clear R after this BD is closed, allowing the buffer to be resent next time the

CPM accesses this BD. However, R is cleared by transmission errors, regardless of CM.

Preamble.

0 No preamble sequence is sent.

1 Before sending data, the controller sends an idle character consisting of all ones. If the data

length of this BD is zero, only a preamble is sent.

No stop bit or shaved stop bit sent.

0 Normal operation. Stop bits are sent with all characters in this buffer.

1 If PSMR[SYN] = 1, data in this buffer is sent without stop bits. If SYN = 0, the stop bit is shaved,

depending on the DSR setting; see Section 21.14, “Fractional Stop Bits (Transmitter).”

9–14

—

Reserved, should be cleared.

CTS lost. The CPM writes this status bit after sending the associated buffer.

0CTS remained asserted during transmission.

1CTS negated during transmission.

Table 21-11. SCC UART TxBD Status and Control Field Descriptions (continued)

Bit

Name

Description

MPC8280 Datasheet(PDF) 725 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 725 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL