MPC8280 datasheet(737/1386 Pages) FREESCALE

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SCC HDLC Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

22-7

22.8

HDLC Mode Register (PSMR)

The protocol-specific mode register (PSMR), shown in Figure 22-3, functions as the HDLC mode register.

Table 22-6 describes PSMR HDLC fields.

Nonoctet

Aligned

Frame

The channel writes the received data to the buffer, closes the buffer, sets RxBD[NO], and generates a

maskable RXF interrupt. CRC error status should be disregarded on nonoctet frames. After a nonoctet

aligned frame is received, the receiver enters hunt mode. An immediate back-to-back frame is still

received. The nonoctet data may be derived from the last word in the buffer as follows:

Note: If buffer swapping is used (RFCR[BO] = 0b0x), the figure above refers to the last byte, rather than

the last word, of the buffer. The lsb of each octet is sent first while the msb of the CRC is sent first.

CRC

The channel writes the received CRC to the buffer, closes the buffer, sets RxBD[CR], generates a

maskable RXF interrupt, and increments the CRC error counter CRCEC. After receiving a frame with a

CRC error, the receiver enters hunt mode. An immediate back-to-back frame is still received. CRC

checking cannot be disabled, but the CRC error can be ignored if checking is not required.

Field

NOF

CRC

RTE

—

FSE

DRT

BUS BRM MFF

—

Reset

R/W

Addr

0x11A08 (PSMR1); 0x11A28 (PSMR2); 0x11A48 (PSMR3); 0x11A68 (PSMR4)

Figure 22-3. HDLC Mode Register (PSMR)

Table 22-6. PSMR HDLC Field Descriptions

Bits

Name

Description

0-3

NOF

Number of flags. Minimum number of flags between or before frames. If NOF = 0b0000, no flags are

inserted between frames and the closing flag of one frame is followed by the opening flag of the next

frame in the case of back-to-back frames. NOF can be modified on-the-fly.

4–5

CRC

CRC selection.

00 16-bit CCITT-CRC (HDLC). X16 + X12 + X5 + 1.

x1 Reserved.

10 32-bit CCITT-CRC (Ethernet and HDLC). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +

X8 + X7 + X5 + X4 + X2 + X1 +1.

RTE

Retransmit enable.

0 No retransmission.

1 Automatic frame retransmission is enabled. Particularly useful in the HDLC bus protocol and

ISDN applications where multiple HDLC controllers can collide. Note that retransmission occurs

only if a lost CTS occurs on the first or second buffer of the frame.

Table 22-5. Receive Errors (continued)

Error

Description

msb

lsb

Valid Data

Nonvalid Data

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