MPC8280 datasheet(738/1386 Pages) FREESCALE

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SCC HDLC Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

22-8

Freescale Semiconductor

22.9

SCC HDLC Receive Buffer Descriptor (RxBD)

The CP uses the RxBD, shown in Figure 22-4, to report on data received for each buffer.

—

Reserved, should be cleared.

FSE

Flag sharing enable. FSE can be set only if GSMR_H[RTSM] is already set. Can be modified

on-the-fly.

0 Normal operation.

1 If NOF[0–3] = 0b0000, a single shared flag is sent between back-to-back frames. Other values of

NOF[0–3] are decremented by 1. Useful in signaling system #7 applications.

DRT

Disable receiver while transmitting.

0 Normal operation.

1 As the SCC sends data, the receiver is disabled and gated by the internal RTS. This helps if the

HDLC channel is on a multidrop line and the SCC does not need to receive its own transmission.

Note: If DRT = 1, GSMR_H[CDS] should be cleared unless both of the following are true: the same

clock is used for TCLK and RCLK, and CTS either has synchronous timing or is always

asserted.

BUS

HDLC bus mode.

0 Normal HDLC operation.

1 HDLC bus operation is selected. See Section 22.14, “HDLC Bus Mode with Collision Detection.”

BRM

HDLC bus RTS mode. Valid only if BUS = 1. Otherwise, it is ignored.

0Normal RTS operation during HDLC bus mode. RTS is asserted on the first bit of the Tx frame

and negated after the first collision bit is received.

1 Special RTS operation during HDLC bus mode. RTS is delayed by one bit with respect to the

normal case, which helps when the HDLC bus protocol is being run locally and sent over a

long-distance line at the same time. The one-bit delay allows RTS to be used to enable the

transmission line buffers so that the electrical effects of collisions are not sent over the

transmission line.

MFF

Multiple frames in Tx FIFO. The receiver is not affected.

0 Normal operation. The Tx FIFO must never contain more than one HDLC frame. The CTS lost

status is reported accurately on a per-frame basis.

1 The Tx FIFO can hold multiple frames, but lost CTS may not be reported on the buffer/frame it

occurred on. This can improve performance of HDLC transmissions of small back-to-back frames

or when the number of flags between frames should be limited.

13–15

—

Reserved, should be cleared.

0123

456

789

Offset + 0

—

Offset + 2

Data Length

Offset + 4

Rx Buffer Pointer

Offset + 6

Figure 22-4. SCC HDLC Receive Buffer Descriptor (RxBD)

Table 22-6. PSMR HDLC Field Descriptions (continued)

Bits

Name

Description

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