MPC8280 datasheet(742/1386 Pages) FREESCALE

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SCC HDLC Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

22-12

Freescale Semiconductor

22.10 SCC HDLC Transmit Buffer Descriptor (TxBD)

The CP uses the TxBD, shown in Figure 22-6, to confirm transmissions and indicate error conditions.

Table 22-8 describes HDLC TxBD status and control fields.

0123

456

Offset + 0

—

—UN

Offset + 2

Data Length

Offset + 4

Tx Buffer Pointer

Offset + 6

Figure 22-6. SCC HDLC Transmit Buffer Descriptor (TxBD)

Table 22-8. SCC HDLC TxBD Status and Control Field Descriptions

Bits

Name

Description

Ready.

0 The buffer is not ready for transmission. Both the buffer and the BD can be updated. The CP

clears R after the buffer is sent or an error is encountered.

1 The buffer has not been sent or is being sent and the BD cannot be updated.

—

Reserved, should be cleared.

Wrap (last BD in TxBD table).

0 Not the last BD in the table.

1 Last BD in the BD table. After this buffer is used, the CP sends data using the BD pointed to by

TBASE. The number of TxBDs in this table is determined by TxBD[W] and the space constraints

of the dual-port RAM.

Interrupt.

0 SCCE[TXB] is not set after this buffer is used; SCCE[TXE] is unaffected.

1 SCCE[TXB] or SCCE[TXE] is set when this buffer is processed, causing interrupts if not masked.

Last.

0 Not the last buffer in the frame.

1 Last buffer in the frame.

Tx CRC. Valid only when TxBD[L] = 1. Otherwise, it is ignored.

0 Transmit the closing flag after the last data byte. This setting can be used to send a bad CRC after

the data for testing purposes.

1 Transmit the CRC sequence after the last data byte.

Continuous mode.

0 Normal operation.

1 The CP does not clear TxBD[R] after this BD is closed allowing the buffer to be resent the next

time the CP accesses this BD. However, TxBD[R] is cleared if an error occurs during

transmission, regardless of CM.

7–13

—

Reserved, should be cleared.

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