MPC8280 datasheet(744/1386 Pages) FREESCALE

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SCC HDLC Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

22-14

Freescale Semiconductor

Figure 22-8 shows interrupts that can be generated using the HDLC protocol.

TXE

Tx error. Indicates an error (CTS lost or underrun) has occurred on the transmitter channel. This event

is not maskable via the TxBD[I] bit.

RXF

Rx frame. Set when the number of receive frames specified in RFTHR are received on the HDLC

channel. It is set no sooner than two clocks after the last bit of the closing flag is received. This event is

not maskable via the RxBD[I] bit.

BSY

Busy condition. Indicates a frame arrived but was discarded due to a lack of buffers.

TXB

Transmit buffer. Enabled by setting TxBD[I]. TXB is set when a buffer is sent on the HDLC channel. For

the last buffer in the frame, TXB is not set before the last bit of the closing flag begins its transmission;

otherwise, it is set after the last byte of the buffer is written to the Tx FIFO.

RXB

Receive buffer. Enabled by setting RxBD[I]. RXB is set when the HDLC channel receives a buffer that

is not the last in a frame.

1 Reserved bits in the SCCE should not be masked in the SCCM register.

Table 22-9. SCCE/SCCM Field Descriptions (continued)1

Bits

Name

Description

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