MPC8280 datasheet(747/1386 Pages) FREESCALE

747 / 1386 page

SCC HDLC Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

22-17

8. Write 0x04A1_0000 to CPCR to execute the INIT RX AND TX PARAMS command for SCC2. This

command updates RBPTR and TBPTR of the serial channel with the new values of RBASE and

TBASE.

9. Write RFCR with 0x10 and TFCR with 0x10 for normal operation.

10. Write MRBLR with the maximum number of bytes per Rx buffer. Choose 256 bytes (MRBLR =

0x0100) so an entire Rx frame can fit in one buffer.

11. Write C_MASK with 0x0000F0B8 to comply with 16-bit CCITT-CRC.

12. Write C_PRES with 0x0000FFFF to comply with 16-bit CCITT-CRC.

13. Clear DISFC, CRCEC, ABTSC, NMARC, and RETRC for clarity.

14. Write MFLR with 0x0100 so the maximum frame size is 256 bytes.

15. Write RFTHR with 0x0001 to allow interrupts after each frame.

16. Write HMASK with 0x0000 to allow all addresses to be recognized.

17. Clear HADDR1–HADDR4 for clarity.

18. Initialize the RxBD. Assume the buffer is at 0x0000_1000 in main memory. RxBD[Status and

Control]= 0xB000, RxBD[Data Length] = 0x0000 (not required), and RxBD[Buffer Pointer] =

0x0000_1000.

19. Initialize the TxBD. Assume the Tx data frame is at 0x0000_2000 in main memory and contains

five 8-bit characters. TxBD[Status and Control] = 0xBC00, TxBD[Data Length] = 0x0005, and

TxBD[Buffer Pointer] = 0x0000_2000.

20. Write 0xFFFF to SCCE to clear any previous events.

21. Write 0x001A to SCCM to enable TXE, RXF, and TXB interrupts.

22. Write 0x0040_0000 to the SIU interrupt mask register low (SIMR_L) so the SMC1 can generate a

system interrupt. Initialize SIU interrupt pending register low (SIPNR_L) by writing

0xFFFF_FFFF to it.

23. Write 0x0000_0000 to GSMR_H2 to enable normal CTS and CD behavior with idles (not flags)

between frames.

24. Write 0x0000_0000 to GSMR_L2 to configure CTS and CD to control transmission and reception

in HDLC mode. Normal Tx clock operation is used. Notice that the transmitter (ENT) and receiver

(ENR) have not been enabled. If inverted HDLC operation is preferred, set RINV and TINV.

25. Write 0x0000 to PSMR2 to configure one opening and one closing flag, 16-bit CCITT-CRC, and

prevent multiple frames in the FIFO.

26. Write 0x00000030 to GSMR_L2 to enable the SCC2 transmitter and receiver. This additional write

ensures that ENT and ENR are enabled last.

NOTE

After 5 bytes and CRC have been sent, the Tx buffer is closed; the Rx buffer

is closed after a frame is received. Frames larger than 256 bytes cause a busy

(out-of-buffers) condition because only one RxBD is prepared.

MPC8280 Datasheet(PDF) 747 Page - Freescale Semiconductor, Inc