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MPC8280 Datasheet(PDF) 750 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 750 Page - Freescale Semiconductor, Inc |
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750 / 1386 page  SCC HDLC Mode MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 22-20 Freescale Semiconductor Figure 22-11. Typical HDLC Bus Single-Master Configuration 22.14.1 HDLC Bus Features The main features of the HDLC bus are as follows: • Superset of the HDLC controller features • Automatic HDLC bus access • Automatic retransmission in case of collision • May be used with the NMSI or a TDM bus • Delayed RTS mode 22.14.2 Accessing the HDLC Bus The HDLC bus protocol ensures orderly bus control when multiple transmitters attempt simultaneous access. The transmitter sending a zero bit at the time of collision completes the transmission. If a station sends out an opening flag (0x7E) while another station is already sending, the collision is always detected within the first byte, because the transmission in progress is using zero bit insertion to prevent flag imitation. While in the active condition (ready to transmit), the HDLC bus controller monitors the bus using CTS. It counts the one bits on CTS. When eight consecutive ones are counted, the HDLC bus controller starts transmitting on the line; if a zero is detected, the internal counter is cleared. During transmission, data is continuously compared with the external bus using CTS. CTS is sampled halfway through the bit time using the rising edge of the Tx clock. If the transmitted bit matches the received CTS bus sample, transmission continues. However, if the received CTS sample is 0 and the transmitted bit is 1, transmission HDLC Controller RXD TXD A RCLK HDLC Bus Controller RXD CTS TXD B HDLC Bus Controller RXD CTS TXD C Clock1 HDLC Bus LAN + 3.3 V R Slave Slave Master NOTES: 1. Transceivers may be used to extend the LAN size. 2. The TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port. 3. Clock1 is the master RCLK and the slave TCLK. Clock2 TCLK RCLK TCLK RCLK TCLK 4. Clock2 is the master TCLK and the slave RCLK. |
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