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MPC8280 Datasheet(PDF) 753 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 753 Page - Freescale Semiconductor, Inc

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SCC HDLC Mode
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
22-23
22.14.5 Using the Time-Slot Assigner (TSA)
HDLC bus controllers can be used with a time-division multiplexed transmission line and a local bus, as
shown in Figure 22-16. Local stations use time slots to communicate over the TDM transmission line;
stations that share a time slot use the HDLC bus protocol to control access to the local bus.
Figure 22-16. HDLC Bus TDM Transmission Line Configuration
The local SCCs in HDLC bus mode communicate only with the transmission line and not with each other.
The SCCs use the TSA of the serial interface, receiving and sending data over L1TXDx and L1RXDx.
Because collisions are still detected from the individual SCC CTS pin, it must be configured to connect to
the chosen SCC. Because the SCC only receives clocks during its time slot, CTS is sampled only during
the Tx clock edges of the particular SCC time slot.
22.14.6 HDLC Bus Protocol Programming
The HDLC bus on the MPC8280 is implemented using the SCC in HDLC mode with bus-specific options
selected in the PSMR and GSMR, as outlined below. See also Section 22.5, “Programming the SCC in
HDLC Mode.”
22.14.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol
To program the protocol-specific mode register (PSMR), set the bits as described below:
•
Configure NOF as preferred
•
Set RTE and BUS to 1
•
Set BRM to 1 if delayed RTS is desired
•
Configure CRC to 16-bit CRC CCITT (0b00).
•
Configure other bits to zero or default.
Local HDLC Bus
HDLC Bus
Controller
L1RXD
CTS
L1TXD
B
HDLC Bus
Controller
L1RXD
CTS
L1TXD
D
+ 3.3 V
R
NOTES:
1. All TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port.
2. The TSA in the SI of each station is used to configure the preferred time slot.
Tx
Rx
Line Driver
HDLC Bus
Controller
L1RXD
CTS
L1TXD
C
HDLC Bus
Controller
L1RXD
CTS
L1TXD
A
Stations share time-slot n
Stations share time-slot m
3. The choice of the number of stations to share a time slot is user-defined. It is two in this example.



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