MPC8280 datasheet(752/1386 Pages) FREESCALE

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SCC HDLC Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

22-22

Freescale Semiconductor

22.14.4 Delayed RTS Mode

Figure 22-14 shows local HDLC bus controllers using a standard transmission line and a local bus. The

controllers do not communicate with each other but with a station on the transmission line; yet the HDLC

bus protocol controls access to the transmission line.

Figure 22-14. HDLC Bus Transmission Line Configuration

Normally, RTS goes active at the beginning of the opening flag’s first bit. Setting PSMR[BRM] delays

RTS by one bit, which is useful when the HDLC bus connects multiple local stations to a transmission line.

If the transmission line driver has a one-bit delay, the delayed RTS can be used to enable the output of the

line driver. As a result, the electrical effects of collisions are isolated locally. Figure 22-15 shows RTS

timing.

Figure 22-15. Delayed RTS Mode

Local HDLC Bus

HDLC Bus

Controller

RXD

CTS

TXD

HDLC Bus

Controller

RXD

CTS

TXD

RTS

+ 3.3 V

NOTES:

1. The TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port.

2. The RTS pins of each HDLC bus controller are configured to delayed RTS mode.

RTS

(1-Bit Delay)

Line Driver

TCLK

RTS active for

only 2 bit times

TXD

CTS

RTS

1st Bit

2nd Bit

3rd Bit

Collision

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