MPC8280 datasheet(746/1386 Pages) FREESCALE

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SCC HDLC Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

22-16

Freescale Semiconductor

Table 22-10 describes HDLC SCCS fields.

22.13 SCC HDLC Programming Examples

The following sections show examples for programming SCCs in HDLC mode. The first example uses an

external clock. The second example implements Manchester encoding.

22.13.1 SCC HDLC Programming Example #1

The following initialization sequence is for an SCC HDLC channel with an external clock. SCC2 is used

with RTS2, CTS2, and CD2 active; CLK3 is used for both the HDLC receiver and transmitter.

1. Configure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and PDIRD[27] and clear

PDIRD[28] and PSORD[27,28].

2. Configure ports C and D pins to enable RTS2, CTS2 and CD2. Set PPARD[26], PPARC[12,13]

and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13] and PSORD[26].

3. Configure port C pin 29 to enable the CLK3 pin. Set PPARC[29] and clear PDIRC[29] and

PSORC[29].

4. Connect CLK3 to SCC2 using the CPM mux. Write 0b110 to CMXSCR[R2CS] and

CMXSCR[T2CS].

5. Connect the SCC2 to the NMSI (its own set of pins). clear CMXSCR[SC2].

6. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and TxBD tables in

dual-port RAM. Assuming one RxBD at the start of dual-port RAM and one TxBD following it,

write RBASE with 0x0000 and TBASE with 0x0008.

7. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and TxBD tables in

dual-port RAM. Assuming one RxBD at the start of dual-port RAM and one TxBD following it,

write RBASE with 0x0000 and TBASE with 0x0008.

Table 22-10. HDLC SCCS Field Descriptions

Bits

Name

Description

0–4

—

Reserved, should be cleared.

Flags. The line is checked after the data has been decoded by the DPLL.

0 HDLC flags are not being received. The most recently received 8 bits are examined every bit time

to see if a flag is present.

1 HDLC flags are being received. FG is set as soon as an HDLC flag (0x7E) is received on the line.

Once it is set, it remains set at least 8 bit times and the next eight received bits are examined. If

another flag occurs, FG stays set for at least another eight bits. If not, it is cleared and the search

begins again.

Carrier sense (DPLL). Shows the real-time carrier sense of the line as determined by the DPLL.

0 The DPLL does not sense a carrier.

1 The DPLL senses a carrier.

Idle status.

0 The line is busy.

1 Set when RXD is a logic 1 (idle) for 15 or more consecutive bit times. It is cleared after a single

logic 0 is received.

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