MPC8280 datasheet(787/1386 Pages) FREESCALE

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SCC Transparent Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

24-13

24.14 SCC2 Transparent Programming Example

The following initialization sequence enables the transmitter and receiver, which operate independently of

each other. They implement the connection shown on MPC8280 (B) in Figure 24-1.

The transmit and receive clocks are externally provided to MPC8280 (B) using CLK3. SCC2 is used. The

transparent controller is configured with the RTS2 and CD2 pins active and CTS2 is configured to be

grounded internally. A 16-bit CRC-CCITT is sent with each transparent frame. The FIFOs are configured

for fast operation.

1. Configure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and PDIRD[27] and clear

PDIRD[28] and PSORD[27,28].

2. Configure ports C and D pins to enable RTS2, CTS2 and CD2. Set PPARD[26], PPARC[12,13]

and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13] and PSORD[26].

3. Configure port C pin 29 to enable the CLK3 pin. Set PPARC[29] and clear PDIRC[29] and

PSORC[29].

4. Connect CLK3 to SCC2 using the CPM mux. Program CMXSCR[R2CS] and CMXSCR[T2CS]

to 0b110.

5. Connect the SCC2 to the NMSI and clear CMXSCR[SC2].

6. Write RBASE with 0x0000 and TBASE with 0x0008 in the SCC2 parameter RAM to point to one

RxBD at the beginning of dual-port RAM followed by one TxBD.

7. Write 0x04A1_0000 to the CPCR to execute INIT RX AND TX PARAMETERS for SCC2.

8. Write 0x0041 to the CPCR to execute INIT RX AND TX PARAMETERS for SCC2.

9. Write RFCR and TFCR with 0x10 for normal operation.

10. Write MRBLR with the maximum number of bytes per receive buffer and assume 16-bytes, so

MRBLR = 0x0010.

11. Write CRC_P with 0x0000_FFFF to comply with the 16-bit CRC-CCITT.

12. Write CRC_C with 0x0000_F0B8 to comply with the 16-bit CRC-CCITT.

13. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000 to

RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to

RxBD[Buffer Pointer].

14. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and contains five

8-bit characters. Write 0xBC00 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and

0x0000_2000 to TxBD[Buffer Pointer].

15. Write 0xFFFF to SCCE to clear any previous events.

16. Write 0x0013 to SCCM to enable the TXE, TXB, and RXB interrupts.

17. Write 0x0040_0000 to the SIU interrupt mask register low (SIMR_L) so SCC2 can generate a

system interrupt. Initialize SIU interrupt pending register low (SIPNR_L) by writing

0xFFFF_FFFF to it.

18. Write 0x0000_1980 to GSMR_H2 to configure the transparent channel.

19. Write 0x0000_0000 to GSMR_L2 to configure CTS and CD to automatically control transmission

and reception (DIAG bits). Normal operation of the transmit clock is used. Note that the transmitter

(ENT) and receiver (ENR) are not enabled yet.

MPC8280 Datasheet(PDF) 787 Page - Freescale Semiconductor, Inc

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