MPC8280 datasheet(785/1386 Pages) FREESCALE

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SCC Transparent Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

24-11

Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).”

Although it is never modified by the CP, data length should be greater than zero. The buffer pointer can be

even or odd and can reside in internal or external memory.

24.12 SCC Transparent Event Register (SCCE)/Mask Register (SCCM)

When the SCC is in transparent mode, the SCC event register (SCCE) functions as the transparent event

is recognized, the transparent controller sets the corresponding SCCE bit. Interrupts are enabled by setting,

and masked by clearing, the equivalent bits in the transparent mask register (SCCM).

Event bits are reset by writing ones; writing zeros has no effect. All unmasked bits must be reset before

the CP clears the internal interrupt request to the SIU interrupt controller. Figure 24-4 shows the event and

mask registers.

Table 24-9 describes SCCE/SCCM fields.

Continuous mode.

0 Normal operation.

1 The CPM does not clear TxBD[R] after this BD is closed, so the buffer is automatically resent

when the CPM accesses this BD next. However, TxBD[R] is cleared if an error occurs during

transmission, regardless of how CM is set.

7–13

—

Reserved, should be cleared.

Underrun. Set when the SCC encounters a transmitter underrun condition while sending the buffer.

CTS lost. Indicates the CTS was lost during frame transmission.

Field

—

DCC

—

GRA

—

TXE

—

BSY

TXB

RXB

Reset

0000_0000_0000_0000

R/W

Addr

0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4)

0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4)

Figure 24-4. SCC Transparent Event Register (SCCE)/Mask Register (SCCM)

Table 24-9. SCCE/SCCM Field Descriptions 1

Bit

Name

Description

0–4

—

Reserved, should be cleared. Refer to note 1 below.

DCC

DPLL CS changed. Set when the DPLL-generated carrier sense status changes (valid only when

the DPLL is used). Real-time status can be read in SCCS. This is not the CD status mentioned

elsewhere.

6–7

—

Reserved, should be cleared. Refer to note 1 below.

Table 24-8. SCC Transparent TxBD Status and Control Field Descriptions (continued)

Bit

Name

Description

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