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MPC8280 Datasheet(PDF) 784 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 784 Page - Freescale Semiconductor, Inc

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SCC Transparent Mode
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
24-10
Freescale Semiconductor
Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).” The
Rx buffer pointer must be divisible by four, unless GSMR_H[RFW] is set to 8 bits wide, in which case the
pointer can be even or odd. The buffer can reside in internal or external memory.
24.11 SCC Transparent Transmit Buffer Descriptor (TxBD)
Data is sent to the CPM for transmission on an SCC channel by arranging it in buffers referenced by the
TxBD table. The CPM uses BDs to confirm transmission or indicate error conditions so the processor
knows buffers have been serviced. Prepare status and control bits before transmission; they are set by the
CPM after the buffer is sent.
Table 24-8 describes SCC Transparent TxBD status and control fields.
0
123
456
789
10
11
12
13
14
15
Offset + 0
R
—
WI
L
TC
CM
—UN
CT
Offset + 2
Data Length
Offset + 4
Tx Buffer Pointer
Offset + 6
Figure 24-3. SCC Transparent Transmit Buffer Descriptor (TxBD)
Table 24-8. SCC Transparent TxBD Status and Control Field Descriptions
Bit
Name
Description
0
R
Ready.
0 The buffer is not ready for transmission. The BD and buffer can be updated. The CPM clears R
after the buffer is sent or after an error is encountered.
1 The user-prepared buffer is not sent yet or is being sent. This BD cannot be updated while R = 1.
1
—
Reserved, should be cleared.
2
W
Wrap (final BD in table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CPM receives incoming data into the first BD
that TBASE points to. The number of TxBDs in this table is determined only by TxBD[W] and
overall space constraints of the dual-port RAM.
3
I
Interrupt. Note that clearing this bit does not disable all SCCE[TXE] events.
0 No interrupt is generated after this buffer is serviced; SCCE[TXE] is unaffected.
1 When the CPM services this buffer, SCCE[TXB] or SCCE[TXE] is set. These bits can cause
interrupts if they are enabled.
4
L
Last in message.
0 The last byte in the buffer is not the last byte in the transmitted transparent frame. Data from the
next transmit buffer is sent immediately after the last byte of this buffer.
1 The last byte in the buffer is the last byte in the transmitted transparent frame. After this buffer is
sent, the transmitter requires synchronization before the next buffer is sent.
5
TC
Transmit CRC.
0 No CRC sequence is sent after this buffer.
1 A frame check sequence defined by GSMR_H[TCRC] is sent after the last byte of this buffer.



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