MPC8280 datasheet(803/1386 Pages) FREESCALE

803 / 1386 page

SCC Ethernet Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

25-15

Table 25-6 describes PSMR fields.

Table 25-6. PSMR Field Descriptions

Bits

Name

Description

HBC

Heartbeat checking.

0 No heartbeat checking is performed. Do not wait for a collision after transmission.

1 Wait 20 transmit clocks or 2 µs for a collision asserted by the transceiver after transmission. The

HB bit in the TxBD is set if the heartbeat is not heard within 20 transmit clocks.

Force collision.

0 Normal operation.

1 The channel forces a collision when each frame is sent. To test collision logic configure the

MPC8280 in loopback operation. In the end, the retry limit for each transmit frame is exceeded.

RSH

Receive short frames.

0 Discard short frames that are not as long as MINFLR.

1 Receive short frames.

IAM

Individual address mode.

0 Normal operation. A single 48-bit physical address in PADDR1 is checked when it is received.

1 The individual hash table is used to check all individual addresses that are received.

4–5

CRC

CRC selection. Only CRC = 10 is valid. Complies with Ethernet specifications. 32-bit CCITT-CRC.

X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 +1.

PRO

Promiscuous.

0 Check the destination address of incoming frames.

1 Receive the frame regardless of its address unless REJECT is asserted as it is being received.

BRO

Broadcast address.

0 Receive all frames containing the broadcast address.

1 Reject all frames containing the broadcast address, unless PRO = 1.

SBT

Stop backoff timer.

0 The backoff timer is functioning normally.

1 The backoff timer for the random wait after a collision is stopped when carrier sense is active.

Retransmission is less aggressive than the maximum allowed in IEEE 802.3. The persistence

(P_PER) feature in the parameter RAM can be used in combination with or in place of SBT.

LPB

Local protect bit

0 Receiver is blocked when transmitter sends (default).

1 Receiver is not blocked when transmitter sends. Must be set for full-duplex operation. For

loopback operation, GSMR[DIAG] must be programmed also; see Section 20.1.1, “The General

SCC Mode Registers (GSMR1–GSMR4).”

—

Reserved. Should be cleared.

LCW

Late collision window.

0 A late collision is any collision that occurs at least 64 bytes from the preamble.

1 A late collision is any collision that occurs at least 56 bytes from the preamble.

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