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MPC8280 Datasheet(PDF) 846 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 846 Page - Freescale Semiconductor, Inc

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Universal Serial Bus Controller
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
27-30
Freescale Semiconductor
Table 27-17 describes USB TrBD fields.
01234
567
8
9
10
11
12
13
14
15
OFFSET + 0x0
R
—
W
I
L
TC
CNF LSP
PID
RXER NAK STAL
TO
UN
BOV
OFFSET + 0x2
DATA LENGTH
OFFSET + 0x4
DATA BUFFER POINTER
OFFSET + 0x6
OFFSET + 0x8
TOK
—
ISO
—
ENDP
ADDR
OFFSET + 0xA
Reserved
Figure 27-21. USB Transaction Buffer Descriptor (TrBD)1,2
1 Entries in boldface must be initialized by the user.
2 All fields should be prepared by the user before transmission.
Table 27-19. USB Host TrBD Fields
Offset
Bit
Name
Description
0x00
0
R
Ready
0 The data buffer associated with this BD is not ready for transmission. The user
is free to manipulate this BD or its associated data buffer. The CP clears this
bit after the buffer has been transmitted or after an error condition is
encountered.
1 The data buffer, which has been prepared for transmission by the user, has not
been transmitted or is currently being transmitted. No fields of this BD may be
written by the user once this bit is set.
1
—
Reserved, should be cleared.
2
W
Wrap (Final BD in Table)
0 This is not the last BD in the TrBD table.
1 This is the last BD in the TrBD table. After this buffer has been used, the CP
will send data using the first BD in the table (the BD pointed to by TBASE).
The number of TrBDs in this table is programmable, and is determined only
by the TrBD[W] and the overall space constraints of the dual-port RAM.
3
I
Interrupt
0 No interrupt is generated after this buffer has been serviced.
1The TXB bit in the event register is set when this buffer is serviced. TXB can
cause an interrupt if it is enabled.
4
L
Last
This bit should always be 1 since each TrBD represents an entire transaction.
5
TC
Transmit CRC. Append CRC to transmitted data packet.
0 Transmit end-of-packet after the last data byte. This setting can be used for
testing purposes to send a bad CRC after the data.
1 Transmit the CRC sequence after the last data byte.
6
CNF
Transmit confirmation.
This bit should always be set to 1 to obtain confirmation for each transaction.
7
LSP
Low-speed transaction.
0 This transaction is with the host or a full-speed device.
1 This transaction is with a low-speed device. Transmit a PRE packet before
the token.



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