MPC8280 datasheet(849/1386 Pages) FREESCALE

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Universal Serial Bus Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

27-33

27.7.2

RESTART Tx Command

This command enables the transmission of data from the corresponding endpoint on the USB. This

command is expected by the USB controller after a STOP Tx Command, or after transmission error

(underrun or time-out).

27.8 USB Controller Errors

The USB controller reports frame reception and transmission error conditions using the BDs and the USB

event register (USBER). Transmission errors are shown in Table 27-20. Errors that exist exclusively in

host mode or function mode are marked as such.

Table 27-21 describes the USB controller reception errors.

Table 27-20. USB Controller Transmission Errors

Error

Description

Transmit

underrun

If an underrun occurs, the transmitter forces a bit stuffing violation, terminates buffer transmission,

closes the buffer, sets TxBD[UN] and the corresponding USBER[TXE

n]. The endpoint resumes

transmission after the RESTART TX ENDPOINT command is received.

Transmit

timeout

Transmit packet not acknowledged. If a timeout occurs, the controller tries to retransmit if

USEP

n[RTE] = 1. If RTE = 0 or the second attempt fails, the controller closes the buffer and sets

TxBD[TO] and USBER[TXE

n]. The endpoint resumes transmission after receiving a RESTART TX

ENDPOINT

command.

Tx data not

ready

For USB function mode only.

This error occurs if an IN token is received, but the corresponding endpoint’s transmit FIFO is empty, or

if the target endpoint is configured to NAK or STALL. The controller sets USBER[TXE

n].

Reception

of NAK or

STALL

hand shake

For USB host mode only.

If this error occurs, the channel closes the buffer, sets the corresponding status bit in the Tx BD (NAK

or STAL), and sets the TXE bit in the USB event register. When using the packet-level interface, the host

will resume transmission after reception of the RESTART TRANSMIT command.

Table 27-21. USB Controller Reception Errors

Error

Description

Overrun Error

If the 16-byte receive FIFO overruns, the previously received byte is overwritten. The controller

closes the buffer and sets both RxBD[OV] and USBER[RXB].

For USB function mode the NAK handshake is sent after the end of the received packet if the

packet was received error-free.

Busy Error

A frame was received and discarded due to lack of buffers. The controller sets USBER[BSY].

Non Octet-Aligned

Packet

If this error occurs, the controller writes the received data to the buffer, closes the buffer and sets

both RxBD[NO] and USBER[RXB].

CRC Error

When a CRC error occurs, the controller closes the buffer, and sets both RxBD[CR] and

USBER[RXB]. In isochronous mode (USEP

n[TM] = 0b11), the USB controller reports a CRC

error; however, there are no handshake packets (ACK) and the transfer continues normally when

an error occurs.

Buffer Overflow

For USB host mode packet-level interface only.

If the received data packet is larger than the allocated buffer, the remaining data is discarded,

and TrBD[BOV] is set. The TXE1 interrupt bit is set.

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