MPC8280 datasheet(865/1386 Pages) FREESCALE

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Serial Management Controllers (SMCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

28-11

28.3.1

Features

The following list summarizes the main features of the SMC in UART mode:

•

Flexible message-oriented data structure

•

Programmable data length (5–14 bits)

•

Programmable 1 or 2 stop bits

•

Even/odd/no parity generation and checking

•

Frame error, break, and idle detection

•

Transmit preamble and break sequences

•

Received break character length indication

•

Continuous receive and transmit modes

28.3.2

SMC UART Channel Transmission Process

The UART transmitter is designed to work with almost no intervention from the core. When the core

enables the SMC transmitter, it starts sending idles. The SMC immediately polls the first BD in the

transmit channel BD table and once every character time after that, depending on character length. When

there is a message to transmit, the SMC fetches data from memory and starts sending the message.

When a BD data is completely written to the transmit FIFO, the SMC writes the message status bits into

the BD and clears R. An interrupt is issued if the I bit in the BD is set. If the next TxBD is ready, the data

from its buffer is appended to the previous data and sent over the transmit signal without any gaps between

buffers. If the next TxBD is not ready, the SMC starts sending idles and waits for the next TxBD to be

ready.

By appropriately setting the I bit in each BD, interrupts can be generated after each buffer, a specific buffer,

or each block is sent. The SMC then proceeds to the next BD. If the CM bit is set in the TxBD, the R bit

is not cleared, allowing a buffer to be automatically resent next time the CP accesses this buffer. For

instance, if a single TxBD is initialized with the CM and W bits set, the buffer is sent continuously until R

is cleared in the BD.

28.3.3

SMC UART Channel Reception Process

When the core enables the SMC receiver, it enters hunt mode and waits for the first character. The CP then

checks the first RxBD to see if it is empty and starts storing characters in the buffer. When the buffer is

full or the MAX_IDL timer expires (if enabled), the SMC clears the E bit in the BD and generates an

interrupt if the I bit in the BD is set. If incoming data exceeds the buffer’s length, the SMC fetches the next

BD, and, if it is empty, continues transferring data to this BD’s buffer. If CM is set in the RxBD, the E bit

is not cleared, so the CP can overwrite this buffer on its next access.

28.3.4

Programming the SMC UART Controller

UART mode is selected by setting SMCMR[SM] to 0b10. See Section 28.2.1, “SMC Mode Registers

(SMCMR1/SMCMR2).” UART mode uses the same data structure as other modes. This structure supports

multibuffer operation and allows break and preamble sequences to be sent. Overrun, parity, and framing

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