MPC8280 datasheet(943/1386 Pages) FREESCALE

943 / 1386 page

Fast Communications Controllers (FCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

30-5

TRX

Transparent receiver. The MPC8280 FCCs offer totally transparent operation. However, to increase

flexibility, totally transparent operation is configured with the TTX and TRX bits instead of the MODE

bits. This lets the user implement unique applications such as an FCC transmitter configured to

HDLC and a receiver configured to totally transparent operation. To do this, program MODE =

HDLC, TTX = 0, and TRX = 1.

0 Normal operation

1 The receiver operates in totally transparent mode, regardless of the protocol selected for the

transmitter in the MODE bits.

Note: Full-duplex, totally transparent operation for an FCC is obtained by setting both TTX and TRX.

Attempting to operate an FCC with Ethernet or ATM on its transmitter and transparent

operation on its receiver causes erratic behavior. In other words, if the MODE = Ethernet or

ATM, TTX must equal TRX.

TTX

Transparent transmitter. The MPC8280 FCCs offer totally transparent operation. However, to

increase flexibility, totally transparent operation is configured with the TTX and TRX bits instead of

the MODE bits. This lets the user implement unique applications, such as configuring an FCC

receiver to HDLC and a transmitter to totally transparent operation. To do this, program MODE =

HDLC, TTX = 1, and TRX = 0.

0 Normal operation.

1 The transmitter operates in totally transparent mode, regardless of the receiver protocol selected

in the MODE bits.

Note: Full-duplex totally transparent operation for an FCC is obtained by setting both TTX and TRX.

Attempting to operate an FCC with Ethernet or ATM on its receiver and transparent operation

on its transmitter causes erratic behavior. In other words, if GFMR[MODE] selects Ethernet

or ATM, TTX must equal TRX.

CDP

CD pulse (transparent mode only)

0 Normal operation (envelope mode). CD should envelope the frame; to negate CD while receiving

causes a CD lost error.

1 Pulse mode. Once CD is asserted (high to low transition), synchronization has been achieved,

and further transitions of CD do not affect reception.

Note: CDP must be set if this FCC is used with the TSA in transparent mode.

CTSP

CTS pulse

0 Normal operation (envelope mode). CTS should envelope the frame; to negate CTS while

transmitting causes a CTS lost error. See Section 30.11, “FCC Timing Control.”

1 Pulse mode. CTS is asserted when synchronization is achieved; further transitions of CTS do not

affect transmission. When running HDLC, the FCC samples CTS only once before sending the

first frame after the transmitter is enabled (ENT = 1).

CDS

CD sampling

0 The CD input is assumed to be asynchronous with the data. The FCC synchronizes it internally

before data is received. (This mode is not allowed in transparent mode when SYNL = 0b00.)

1 The CD input is assumed to be synchronous with the data, giving faster operation. In this mode,

CD must transition while the receive clock is in the low state. When CD goes low, data is received.

This is useful when connecting MPC8280s in transparent mode since it allows the RTS signal of

one MPC8280 to be connected directly to the CD signal of another MPC8280.

Table 30-2. GFMR Register Field Descriptions (continued)

Bits

Name

Description

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