MPC8280 datasheet(947/1386 Pages) FREESCALE

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Fast Communications Controllers (FCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

30-9

30.5

FCC Transmit-on-Demand Registers (FTODR

If no frame is being sent by the FCC, the CP periodically polls the R bit of the next TxBD to see if the user

has requested a new frame/buffer to be sent. Polling occurs every 256 serial transmit clocks. The polling

algorithm depends on the FCC configuration, as shown in the following equations:

The user, however, can request that the CP begin processing the new frame/buffer without waiting the

normal polling time. For immediate processing, after setting TxBD[R], set the transmit-on-demand (TOD)

bit in the transmit-on-demand register (FTODR) twice to activate. If TOD is set only once, the new

frame/buffer will not be transmitted until the next periodic polling request.

This feature, which decreases the transmission latency of the transmit buffer/frame, is particularly useful

in LAN-type protocols where maximum interframe GAP times are limited by the protocol specification.

Since the transmit-on-demand feature gives a high priority to the specified TxBD, it can conceivably affect

the servicing of the other FCC FIFO buffers. Therefore, it is recommended that the transmit-on-demand

feature be used only for a high-priority TxBD and when transmission on this FCC has not occurred for a

given time period, which is protocol-dependent.

If a new TxBD is added to the BD table while preceding TxBDs have not completed transmission, the new

TxBD is processed immediately after the older TxBDs are sent.

Fields in the FTODR are described in Table 30-4.

Field

SYN2

SYN1

Reset

R/W

Addr

0x1130C (FDSR1), 0x1132C (FDSR2), 0x1132C (FDSR3)

Figure 30-4. FCC Data Synchronization Register (FDSR)

Field TOD

—

Reset

0000_0000_0000_0000

R/W

Addr

0x11308 (FTODR1), 0x11328 (FTODR2), 0x11348 (FTODR3)

Figure 30-5. FCC Transmit-on-Demand Register (FTODR)

Fast Ethernet:

256 clocks / 25 MHz = 10

µs

10BaseT:

256 clocks / 2.5 MHz = 100

µs

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