MPC8280 datasheet(951/1386 Pages) FREESCALE

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Fast Communications Controllers (FCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

30-13

0x0C

RBASE

Word

RxBD base address (must be divisible by eight). Defines the starting location in the

memory map for the FCC RxBDs. This provides great flexibility in how FCC RxBDs are

partitioned. By selecting RBASE entries for all FCCs and by setting the W bit in the last

BD in each BD table, the user can select how many BDs to allocate for the receive side

of every FCC. The user must initialize RBASE before enabling the corresponding

channel. Furthermore, the user should not configure BD tables of two enabled FCCs to

overlap or erratic operation occurs.

0x10

RBDSTAT

Hword RxBD status and control. Reserved for CP use only.

0x12

RBDLEN

Hword RxBD data length. A down-count value initialized by the CP with MRBLR and

decremented with every byte written by the SDMA channels.

0x14

RDPTR

Word

RxBD data pointer. Updated by the SDMA channels to show the next address in the buffer

to be accessed.

0x18

TSTATE

Word

Tx internal state. The high byte, TSTATE[0–7], contains the function code register; see

Section 30.7.1, “FCC Function Code Registers (FCRx).” TSTATE[8–31] is used by the CP

and must be cleared initially.

0x1C

TBASE

Word

TxBD base address (must be divisible by eight). Defines the starting location in the

memory map for the FCC TxBDs. This provides great flexibility in how FCC TxBDs are

partitioned. By selecting TBASE entries for all FCCs and by setting the W bit in the last

BD in each BD table, the user can select how many BDs to allocate for the transmit side

of every FCC. The user must initialize TBASE before enabling the corresponding channel.

Furthermore, the user should not configure BD tables of two enabled FCCs to overlap or

erratic operation occurs.

0x20

TBDSTAT

Hword TxBD status and control. Reserved for CP use only.

0x22

TBDLEN

Hword TxBD data length. A down-count value initialized with the TxBD data length and

decremented with every byte read by the SDMA channels.

0x24

TDPTR

Word

TxBD data pointer. Updated by the SDMA channels to show the next address in the buffer

to be accessed.

0x28

RBPTR

Word

RxBD pointer. Points to the next BD that the receiver transfers data to when it is in idle

state or to the current BD during frame processing. After a reset or when the end of the

BD table is reached, the CP sets RBPTR = RBASE. Although the user need never write

to RBPTR in most applications, the user can modify it when the receiver is disabled or

when no receive buffer is in use.

0x2C

TBPTR

Word

TxBD pointer. Points either to the next BD that the transmitter transfers data from when it

is in idle state or to the current BD during frame transmission. After a reset or when the

end of the BD table is reached, the CP sets TBPTR = TBASE. Although the user need

never write to TBPTR in most applications, the user can modify it when the transmitter is

disabled or when no transmit buffer is in use (after a STOP TRANSMIT or GRACEFUL STOP

TRANSMIT

command is issued and the frame completes transmission).

0x30

RCRC

Word

Temporary receive CRC

0x34

—

Word

Reserved

0x38

TCRC

Word

Temporary transmit CRC

0x3C

—

Word

First word of protocol-specific area

Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 14.5.2, “Parameter RAM.”

Table 30-5. FCC Parameter RAM Common to All Protocols Except ATM (continued)

Offset1

Name

Width

Description

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