MPC8280 datasheet(952/1386 Pages) FREESCALE

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Fast Communications Controllers (FCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

30-14

Freescale Semiconductor

30.7.1

FCC Function Code Registers (FCR

The function code registers contain the transaction specification associated with SDMA channel accesses

to external memory. Figure 30-8 shows the format of the transmit and receive function code registers,

which reside at TSTATE[0–7] and RSTATE[0–7] in the FCC parameter RAM (see Table 30-5).

FCRx fields are described in Table 30-6.

30.8

Interrupts from the FCCs

Interrupt handling for each of the FCC channels is configured on a global (per channel) basis in the

interrupt pending register (SIPNR_L) and interrupt mask register (SIMR_L). One bit in each register is

used to either mask, enable, or report an interrupt in an FCC channel. The interrupt priority between the

FCCs is programmable in the CPM interrupt priority register (SCPRR_H). The interrupt vector register

01234567

Field

—

FCCP

GBL

TC2

DTB

BDB

Figure 30-8. Function Code Register (FCR

Table 30-6. FCR

x Field Descriptions

Bits

Name

Description

—

Reserved, should be cleared.

FCCP

FCC priority. Used in conjunction with PPC_ACR[PRKM] (see section 4.3.2.2) and

LCL_ACR[PRKM] (see section 4.3.2.4) for a low request level.

Disables CPM low request level to refer to FCCs and MCCs.

Enables CPM low request level to refer to FCCs and MCCs.

GBL

Global. Indicates whether the memory operation should be snooped.

0 Snooping disabled.

1 Snooping enabled.

3–4

Byte ordering. Used to select the byte ordering of the buffer. If BO is modified on-the-fly, it takes

effect at the start of the next frame (Ethernet, HDLC, and transparent) or at the beginning of the next

BD.

01 Munged little-endian byte ordering. As data is sent onto the serial line from the data buffer, the

LSB of the buffer double-word contains data to be sent earlier than the MSB of the same buffer

double-word.

10 Freescale byte ordering (normal operation). It is also called big-endian byte ordering. As data is

sent onto the serial line from the data buffer, the MSB of the buffer word contains data to be sent

earlier than the LSB of the same buffer word.

TC2

Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory

access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.

DTB

Indicates on what bus the data is located.

On the 60x bus.

On the local.

BDB

Indicates on what bus the BDs are located.

On the 60x bus.

On the local bus.

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